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參數(shù)資料
| 型號： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 28/76頁 |
| 文件大?。?/td> | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
28
Datasheet
4.2.2.1
J2 Memory Access
The J2 RAM for each tributary is indirectly accessible by the microprocessor. That is, there is a
single data port to access the data, while the address is internally generated and automatically
incremented as the J2 RAM byte is read or written. The following procedure should be followed to
correctly program the J2 RAM.
Ensure that XmtJ2Access is set to
‘
1
’
in
“
ERRI_CONF
—
Error Insert Configuration (xDH)
”
on page 58
.
Write (any value) to J2_MRST-- J2 Memory reset
(008H) page 50. This resets the global
counter used to generate the RAM address. This step is only required once if multiple
tributaries are being programmed.
Write the 16 bytes of the J2 word consecutively to
“
J2_TSDATA
—
J2 Transmit String Data
(xFH)
”
on page 58
. Each toggle of the write (or read) will increment the internal counter in
DMA fashion
If write verification is desired, the microprocessor can now read 16 bytes in DMA fashion. The
internal address counter resets to 0 after the 16 writes.
Once the RAM is filled and verified, the XmtJ2Access bit can be set to
‘
0
’
to enable the
transmit J2 word.
All 16 bytes are written to the RAM by the microprocessor. This places a requirement on the
microprocessor that it must calculate the CRC-7 byte on the 15 byte Path Trace ID and write the
calculated CRC-7 byte in the first position of the J2 RAM.
4.2.3
K4 Processing
The chip supports generation of the enhanced RDI function if the TxK4En configuration bit is set
in
“
GLOB_CONF
—
Global Configuration (000H)
”
on page 55
. All other bits in the K4 byte will
be set to
‘
0
’
. The alarm status received on the RAP port will drive the K4 byte as follows:
The forced RDI condition is set by setting the XmtLptRdiFrc bit in
“
ERRI_CONF
—
Error Insert
Configuration (xDH)
”
on page 58
to
‘
1
’
.
4.2.4
N2 Processing
N2 processing is not implemented at this time. The transmitted value for the N2 byte is
‘
00000000
’
.
Table 5. Enhanced RDI Generation
K4, bit 5
K4, bit 6
K4, bit 7
Alarm
0
0
0
No Alarm or TxK4En not
set
1
0
1
TU-AIS, TU-LOP
1
1
0
TIM, UNEQ
1
1
1
Forced RDI Alarm
NOTE:
The bit numbers above reference a byte whose least
significant bit is bit 8
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