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參數(shù)資料
| 型號(hào)： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁(yè)數(shù)： | 67/76頁(yè) |
| 文件大?。?/td> | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
67
9.1.1
Instruction Register and Definitions
The LXT6251A supports the following instructions IEEE1149.1: EXTEST, SAMPLE/PRELOAD,
BYPASS and IDCODE. Instructions are shifted into the instruction register during the SHIFT-IR
state, and become active upon exiting the UPDATE-IR state. The instruction register definition is
shown in the following figure.
9.1.1.1
EXTEST (
‘
b00)
This instruction allows the testing of circuitry external to the package, typically the board
interconnect, to be tested. While the instruction is active, the boundary scan register is connected
between TDI and TDO, for any data shifts. Boundary scan cells at the output pins are used to apply
test stimuli, while those at input pins capture test results. Signals present on input pins are loaded
into the BSR inputs cells on the rising edge of JTCK during CAPTURE-DR state. BSR contents are
shifted one bit location on each rising edge of JTCK during the SHIFT-DR state. BSR output cell
contents appear at output pins on the falling edge of JTCK during the UPDATE-IR state.
One test cycle is:
1. A test stimuli pattern is shifted into the BSR during SHIFT-DR state.
2. This pattern is applied to output pins during the UPDATE-DR state.
3. The response is loaded into the input BSR cells during the CAPTURE-DR state.
Figure 20. Test Access Port
Boundary Scan
Bypass Register
Device ID register
Instruction Register
JTDI
TDO
Test Access
Port Controller
JTMS
JTCK
JTRS
Figure 21. Instruction Register
TDI
MSB
LSB
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