參數(shù)資料
型號(hào)： LXT6251A
英文描述： ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC
中文描述： 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料
文件頁數(shù)： 5/76頁
文件大?。?/td> 995K
代理商： LXT6251A
Datasheet
5
21 E1 SDH Mapper
—
LXT6251A
8.5.1
8.5.2
8.5.3
8.5.4
Status and Control Registers ..............................................................................63
8.6.1
TRIB_STA
—
Tributary Status (x3
–
x2H)..................................................63
8.6.2
BIP2_ERRCNT
—
BIP2 Error Counter (x7
–
x6H).....................................63
8.6.3
REI_CNT
—
Remote Error Indication (REI) Counter (x9
–
x8H)................64
8.6.4
K4_STA
—
K4 Status (xAH).....................................................................64
8.6.5
V5_STA
—
V5 Status Register (xBH) ......................................................64
Testability Modes
.....................................................................................................66
9.1
IEEE 1149.1 Boundary Scan Description............................................................66
9.1.1
Instruction Register and Definitions........................................................67
9.1.1.1 EXTEST (
‘
b00) ..........................................................................67
9.1.1.2 SAMPLE/PRELOAD (
‘
b01) .......................................................68
9.1.1.3 BYPASS (
‘
b11)..........................................................................68
9.1.1.4 IDCODE (
‘
b10) ..........................................................................68
9.1.2
Boundary Scan Register ........................................................................68
Package Specification
............................................................................................75
Glossary
.......................................................................................................................76
GLOB_INTS
—
Global Interrupt Source (00CH)......................................60
TRIB_ISRC
—
Tributary Interrupt Source Identification (00F
–
00DH)......60
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)................................................61
TRIB_INTE
—
Tributary Interrupt Enable (x5
–
x4H).................................62
8.6
9.0
10.0
11.0
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
LXT6251A Block Diagram.....................................................................................7
LXT6251A Pin Assignments..................................................................................8
LXT6251A Block Diagram...................................................................................17
V1/V2 Pointer Diagram........................................................................................18
V5 Byte................................................................................................................19
Add/Drop Configuration Data Flow......................................................................31
ADM Multi-chip Configuration..............................................................................33
STM-0 Telecom Bus Timing................................................................................38
Terminal STM-1 Telecom Bus Timing (...............................................................39
ADM STM-1 Telecom Bus Timing w/ PTSOH=1.................................................39
ADM STM-1 Telecom Bus Timing w/ PTSOH = 0...............................................40
SAP Bus Connections for Terminal & ADM ........................................................41
SAP Bus Frame Format......................................................................................41
Tributary Timing ..................................................................................................43
Receive Telecom Bus Timing..............................................................................44
Transmit Telecom Bus Timing - Terminal ...........................................................45
Transmit Telecom Bus Timing - ADM Parameters..............................................46
Microprocessor Data Read Timing......................................................................47
Microprocessor Data Write Timing......................................................................48
Test Access Port.................................................................................................67
Instruction Register .............................................................................................67
Boundary Scan Cells...........................................................................................69
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