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參數(shù)資料
| 型號(hào)： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 51/76頁 |
| 文件大?。?/td> | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
51
When a multiplexed data/address bus is used, the falling edge of the AS input latches the address
provided on A<8:0>. If the address and data are not multiplexed the AS pin should be tied High.
Timing diagrams for the Intel interface can be found in
Figure 18
and
Figure 19
starting on page
page 47
.
8.2
Interrupt Handling
There are 21 tributaries that are each capable of generating 13 alarms. Any one of these alarms (if
enabled) can cause the device interrupt pin to become active.
Each tributary has three registers associated with it:
Interrupt source: These registers identify the source of the interrupt(s).
Alarm status: These registers provide the current status of alarm monitoring hardware
processes.
Interrupt Enable: These registers enable interrupt sources to affect the state of the INT pin.
8.2.1
Interrupt Sources
There are three types of interrupt sources:
Status alarm changes: Any time a status alarm changes state, an interrupt bit is set. For
example, the LXT6251A monitors the incoming V5 RDI bit. A hardware process monitors this
bit for changes and sets bit 3 in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
when
the change persists for 5 frames.
Event Alarms: Any time a momentary event alarm occurs, an interrupt bit is set. For example,
the LXT6251A monitors the incoming V5 byte for a change in its REI bit from a
‘
0
’
to a
‘
1
’
.
Such an event will SET bit 5 in interrupt register
x
0H.
Counter overflows: The LXT6251A monitors the incoming V5 to see if it
’
s REI bit is set.
Each multiframe with the REI bit set causes an REI counter to be incremented. If the counter
overflows, bit 4 of interrupt register
x
0H is set.
8.2.1.1
Interrupt Identification
There are four registers used to identify the source of an interrupt. The Global Interrupt Source
register provides three bits to identify tributaries 1-8, 9-14, or 15-21. After the group is determined,
there are three associated Tributary ID registers to indicate the tributary which caused the alarm.
8.2.2
Interrupt Enables
In order for an interrupt source to affect the state of the INT output pin, its associated interrupt
enable bit must be set. The setting (whether it is 0 or 1) of the interrupt enables does not affect the
updating of the interrupt, status, overhead byte or counter registers.
Assuming the interrupt enable for a particular interrupt source is SET and the interrupt source is
active, the INT output pin will be activated.
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