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參數(shù)資料
| 型號： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 15/76頁 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
15
27
AS
TTLin
Address Latch Enable
. Used by chip for systems where address and
data busses are multiplexed. Latches A<8:0> on the falling edge. If
address and data are not multiplexed, this pin should be tied High.
JTAG Boundary Scan Test Functions
148
SCANTEST
TTLin-48PU
Active Low Scan Test mode select with ~48 KOhm Pull-up resistor.
Should be left unconnected for normal operation.
160
SCANEN
ITTLin-48PU
Active Low Scan Enable with ~48 KOhm Pull-up resistor. Controls all
Scan FF muxes. Should be left unconnected for normal operation.
153
JTCK
I
TTLin-48PU
JTAG Clock.
This signal has a ~48 K
Pull-up resistor. Clock for the
boundary scan circuitry. See
“
IEEE 1149.1 Boundary Scan
Description
”
on page 66
for details.
152
JTMS
I
TTLin-48PU
Test Mode Select.
This signal has a ~48K
Pull-up resistor. This pin
determine state of TAP controller.
151
JTRS
I
TTLin-35PD
Active low Reset.
This signal has a ~35K
Pull-down resistor.
Should be left unconnected for normal device usage.
150
JTDI
ITTLin-48PU
Data Input.
This signal has a ~48K
Pull-up resistor. Input signal
used to shift in instructions and data. Should be left unconnected for
normal device usage.
149
JTDO
O
HiZ-2mA
Data Output.
Output signal used to shift out instruction and data.
Control Functions
154
OEN
I
TTLin-48PU
Output Enable.
This signal has a ~48KOhm Pull-up resistor. Used to
disable all output pins for bed of nails type testing or other
applications. When Low, all outputs are in high impedance and all bi-
directional pins are inputs. Should be left unconnected for normal
operation.
33
RST
I
TTLin-108PUS
Chip Master Reset.
This signal has a ~108KOhm Pull-up resistor. A
low will reset all registers to default conditions. Input logic is a schmidt
trigger type.
32
STMMODE
I
TTLin
STM Mode Select.
Low = STM-0, High = STM-1
Table 3. Power, Ground, and No Connects
Pin #
Name
Type
Power Supply
12, 34, 66, 91, 118, 139, 170, 195
VCC_5
5V Supply for I/O ring
1, 13, 23, 52, 53, 77, 80, 104, 105, 128, 156,
157, 181, 187, 208
GND_5
GND 5 Volts.
Ground pins for 5 Volt supply
.
24, 50, 78, 102, 103, 131, 155, 183, 184, 206,
207
VCC_3
3 V supply for core
3, 25, 54, 55, 79, 106, 132, 158, 159, 185,
186
GND_3
GND 3 Volts.
Ground pins for 3 Volt supply
.
2, 41, 51, 171, 173, 182, 192, 194
NC
Not Connected.
Unused
Table 2. Pin Descriptions (Continued) (Sheet 7 of 7)
Pin #
Name
Type
Function
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