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參數(shù)資料
| 型號： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 18/76頁 |
| 文件大小： | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
18
Datasheet
3.3
High Order Path Adaptation
Within each of the 21 TU-12 demapper blocks, the telecom bus data bytes first enter the higher
order path adaptation (HPA) block for TU-12 pointer interpretation. The TU-12 pointer is
contained in the V1 and V2 bytes shown below. The 8 bits of V2 and the 2 LSB bits of V1, shown
as I and D bits, represent a binary number that represents the number of TU-12 bytes between the
V5 POH byte and V2. The SS bits identify Tributary type, and the remaining 4 bits represent a New
Data Flag (NDF). Based on the incoming J0J1, Payload, and H4 timing signals, the V1 and V2
bytes are located and interpreted. The pointer interpreter state machine follows the state diagram
provided in the Appendix of ITU-T G.783. The variable N in that specification, which specifies the
number of invalid pointers required to enter the Loss of Pointer state, is set to eight (8) in the
LXT6251A. When a valid pointer is found (a valid pointer defined as being between the values 0
and 139), the pointer processing block will synchronize the TU timing block and remove the Loss
of Pointer (LOP) alarm.
After achieving a normal pointer state, the processor will continually monitor V1 and V2 for the
following events:
Positive Justification from the inversion of the I bits (3 of 5 majority decision)
Negative Justification from the inversion of the D bits (3 of 5 majority decision)
New pointer value from 3 new valid values in a row
New pointer value from single NDF indication (if in Normal or AIS state only)
All 1
s condition on the V1/V2 bytes
Invalid pointer values occurring 8 times in a row to trigger a LOP alarm
Reception of NDF indication 8 times in a row to trigger a LOP alarm
3.3.1
Alarms and Status
3.3.1.1
TU-AIS
If 3 consecutive TU pointers in the all 1
’
s (AIS) state are detected, the TU-AIS status bit in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on page 63
is set. It is cleared when either the LOP or
Normal states are entered. Whenever the TU-AIS status changes the TU-AIS interrupt bit in
“
TRIB_INT
—
Tributary Interrupt (x1
–
x0H)
”
on page 61
is set.
Consequent Actions:
An RDI Indication will be sent to the transmitter via the SAP interface. The RDI indication
will be set on the transmitted V5 byte unless the XmtLptRdiEn bit in
“
ERRI_CONF
—
Error
Insert Configuration (xDH)
”
on page 58
is set to 0
Outgoing E1 data on DTDx will be forced to AIS with derived 2.048MHz clock on DTCx
Figure 4. V1/V2 Pointer Diagram
I
I
D
D
I
I
D
D
NDF
S
I
S
D
NDFNDF
4
V1
V2
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
NDF
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