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參數(shù)資料
| 型號： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 13/76頁 |
| 文件大?。?/td> | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
13
204-197
MTBDATA <7:0>
O
HiZ - 4mA
Multiplex Telecom Bus Data 7 to 0.
This is a byte wide data output
at 19.44 Mbit/s for STM-1 or 6.48 Mbit/s for STM-0. The output in
STM-1 may be tri-stated for certain bytes depending on the
configuration of the device.
196
MTBPAR
O
HiZ - 4mA
Multiplex Telecom Bus Parity.
This is the parity check signal
calculated on the MTBDATA byte only. It is an odd parity and is
always a calculated value (i.e. the value is not passed through in
ADM).
193
MTBYCK
I
TTLin
Multiplexer Telecom Bus Clock.
This clock drives the multiplexer
section at 6.48 MHz for STM-0 or 19.44MHz for STM-1.
191
MTBJ0J1EN
I/O
TTLin - 4mA
Multiplex Telecom Bus Frame indicator.
This indicates the
presence of the J0 and J1 bytes on the MTBDATA bus. Optionally
configurable to also indicate H4 multiframe position, instead of using
MTBH4EN.
188
MTBH4EN
I/O
TTLin - 4mA
Multiplex Telecom Bus H4 multiframe Indicator.
An output in ADM
mode, this is a 2 KHz signal that indicates the location of the 00 value
of H4. As input in terminal mode, the signal is sampled during the J1
byte position given by MTBJ0J1EN.
189
MTBPAYEN
I/O
TTLin - 4mA
Multiplex Telecom Bus Payload Enable.
Indicates the position of
VC-4 in the STM-1 mode or VC-3 in the STM-0 mode. In an ADM
configuration the pin is an output while in the terminal mode it is an
input.
190
MTBTUGEN
I
TTLin
Multiplexer Telecom Bus TUG Enable.
This pin is used in STM-1
terminal applications and controls the TUG-3 in which the LXT6251A
will generate data. This pin should be tied to Vcc for STM-0 terminal
applications.
205
MTBDOE
O
HiZ - 4mA
Multiplexer Telecom Bus Output Enable.
Active Low output enable
signal that mirrors the internal MTBDATA data bus control. Its function
is to enable an
external
tri-state bus driver that should be used when
the device is installed in a multi-card/backplane environment. Usually
reserved for STM-1 use, the signal is always active in STM-0
161 - 168
DTBDATA <7:0>
I
TTLin
Demultiplexer Telecom Bus Data 7.
This is a byte wide data input at
19.44 Mbit/s for STM-1 or 6.48 Mbit/s for STM-0. In STM-1 mode, the
data is ignored if DTBTUGEN is Low.
169
DTBPAR
I
TTLin
Telecom Bus Parity.
This is parity check calculated on the
DTBDATA byte only. It is an odd parity.
172
DTBYCK
I
TTLin
Demultiplexer Telecom Bus Clock.
This clock drives the
demultiplexer section at 6.48 MHz for STM-0 or 19.44MHz for STM-1
174
DTBJ0J1EN
I
TTLin
Demultiplexer Telecom Bus Frame Indicator.
This indicates the
position of J0 and J1 bytes on the DTBDATA bus. Optionally
configurable to also detect H4 multiframe position, instead of using
DTBH4EN.
180
DTBH4EN
I
TTLin
Demultiplexer Telecom Bus H4 multiframe Indicator.
This is a 2
KHz signal that indicates the location of the 00 value of H4. This
signal is sampled during the J1 pulse from DTBJ0J1EN.
179
DTBPAYEN
I
TTL-in
Demultiplexer Telecom Bus Payload Enable.
Indicates the position
of VC-4 in the STM-1 mode or VC-3 in the STM-0 mode. This pin is
always an input.
175
DTBTUGEN
I
TTLin
Demultiplexer Telecom Bus TUG Enable.
This pin is used in STM-1
applications and indicates the proper TUG-3 payload the
demultiplexer section should process. This pin is tied to VCC for STM-
0 applications.
Table 2. Pin Descriptions (Continued) (Sheet 5 of 7)
Pin #
Name
Type
Function
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