參數(shù)資料
型號(hào)： LXT6251A
英文描述： ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC
中文描述： 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料
文件頁(yè)數(shù)： 35/76頁(yè)
文件大?。?/td> 995K
代理商： LXT6251A
21 E1 SDH Mapper
—
LXT6251A
Datasheet
35
6.2
Telecom Bus Interface
The LXT6251A uses an industry standard Telecom Bus to interface with other SDH products,
including LXT6051. The standard is based on the original work of the IEEE P1396 project that
never made it to final approval. Intel has enhanced the bus to be compatible with other standard
SDH products on the market.
6.2.1
Multiplexer Telecom Bus, Terminal Mode
In terminal mode, the multiplexer side Telecom Bus operates in a contra-directional mode,
meaning the Mapper receives the timing signals and generates the Data synchronized to the timing
signals but delayed by one half clock cycle. Functional Timing diagrams are shown in Figure 7 and
Figure 8.
MTBYCK
Input Telecom Bus byte clock at 6.48 MHz for STM0 or 19.44 MHz for
STM1.
MTBDATA
Output Byte parallel Data. In STM-0, the data consists of the 21 TU-12
signals in a 7 by TUG-2 format plus the 2 fixed stuff columns of a C3
container at positions 30 and 59. The data bus is also driven during all
other SOH and HPOH bytes, however, the data during these times is not
valid. In STM-1, the data consists of a single TUG-3 payload controlled by
MTBTUGEN. The bus is in tri-state for all other bytes (SOH, HPOH, fixed
stuff)
MTBPAR
Output parity bit calculated on each output MTBDATA byte. This is an odd
parity calculation.
MTBJ0J1EN
Input Frame Position indicator, active high during both the J0 and J1
bytes. The J0 byte is identified when the MTBPAYEN is low, J1 when
MTBPAYEN is high. Optionally the MultiFrmSel configuration bit in
“
GLOB_CONF
—
Global Configuration (000H)
”
on page 55
can be set to
‘
1
’
, which adds a multiframe indication (byte H4=00 for TU-12 V1 byte
location) by detecting a two-byte wide J1 pulse every fourth frame. Note
the H4 indication can be active even when MTBPAYEN is Low.
MTBPAYEN
Input Payload Enable. A high on this input enables the driving of the
MTBDATA bus with the VC-3 or VC-4 payload. A low indicates the
location of the SOH bytes and the AU Pointers bytes.
MTBH4EN
Input indicates the multiframe start position. This signal must be active
high during the J1 byte following the multiframe when the H4 byte equals
15
16Fh
15
15
(1, 3)
16
170h
16
16
(2, 3)
17
171h
17
17
(3, 3)
18
172h
18
18
(4, 3)
19
173h
19
19
(5, 3)
20
174h
20
20
(6, 3)
21
175h
21
21
(7, 3)
Table 7. E1 Port Time Slot Assignment (Continued)
Tributary Circuit (Port)
Register Address
Default Value
Default
Time Slot
TU-12 Address (L, M)
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