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參數(shù)資料
| 型號： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 995K |
| 代理商： | LXT6251A |
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LXT6251A
—
21 E1 SDH Mapper
22
Datasheet
3.4.2.1
J2 Memory Access
The J2 RAM for each tributary is indirectly accessible by the microprocessor. That is, there is a
single data port to access the data, while the address is internally generated and automatically
incremented as the J2 RAM byte is read or written. The following procedure should be followed to
correctly program the J2 RAM.
Ensure that RxJ2Access is set to
‘
1
’
in
“
TRIB_INTE
—
Tributary Interrupt Enable (x5
–
x4H)
”
on page 62
.
Write (any value) to J2_MRST-- J2 Memory reset
(008H) page 50. This resets the global
counter used to generate the RAM address. This step is only required once if multiple
tributaries are being programmed.
Write the 16 bytes of the J2 word consecutively to
“
J2_ESDATA
—
J2 Expected String Data
(xCH)
”
on page 58
. Each toggle of the write (or read) will increment the internal counter in
DMA fashion.
If write verification is desired, the microprocessor can now read 16 bytes in DMA fashion. The
internal address counter resets to 0 after the 16 writes.
Once the RAM is filled and verified, the RxJ2Access bit can be set to
‘
0
’
to enable the alarms.
Note that all 16 bytes should be written to the RAM by the microprocessor. The CRC-7 byte is not
needed in the receiver RAM (the received CRC-7 byte is compared with a calculated value only),
however the microprocessor must write some value on the first write to align the remaining 15
words in the RAM.
During normal operation with J2 support, the RxJ2Access bit should be set to
‘
0
’
, allowing the
alarms associated with J2 to be generated. As data is received, each J2 byte is analyzed until the
CRC-7 byte is found, which is distinguished from the other 15 bytes by having a 1 in the most
significant bit. The CRC-7 byte is stored, then the following 15 bytes are used to calculate a CRC-
7 value and compared with successive locations in the RAM. The CRC-7 byte is never compared
with the contents of the J2 RAM.
Two alarms can be generated: the Trace Identifier Mismatch (TIM) and the CRC-7 mismatch
(CRC7).
3.4.2.2
CRC-7 Error
The chip calculates the CRC-7 value over the 15 bytes of the received J2 string. This value will be
compared with the received CRC-7 byte. If the calculated and received CRC-7 bytes do not match,
the J2 CRC-7 error (CRC7Err) status bit is set in
“
TRIB_STA
—
Tributary Status (x3
–
x2H)
”
on
page 63
. If the calculated and received CRC-7 bytes do match, the CRC7Err status bit is cleared.
Whenever the CRC7Err status bit changes the CRC7Err interrupt bit in
“
TRIB_INT
—
Tributary
Interrupt (x1
–
x0H)
”
on page 61
is set.
Consequent Actions: none
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