- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360706 > IBM32NPR100EXXCAB133 Microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM32NPR100EXXCAB133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 91/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR100EXXCAB133 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)當(dāng)前第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Reset, Initialization, and Operation
Page 91 of 131
3. Sync Status and Sync Hunt registers 0x’08‘
4. Sync Packet Transmit register 0x’09‘
5. Signal detect Interrupt in Status register bit 12
The Sync Status register reports the status of the input receiver, and the Sync Hunt register forces the input
ports to start the synchronization sequence.
The Sync Packet Transmit register specifies on which port the sync packets are to be transmitted in order for
the remote device input port to synchronize. While sync packets are transmitted on an output port, Data
Packets destined to that output port will be discarded at the same rate as if they were actually sent on the
line. When not transmitting Sync packets, the output ports transmit normal traffic packets, Data Packets or
Idle Packets.
Also, when the PRS28.4G is used in external speed expansion, the local processor must set the Sync Hunt
register and check the Sync Status register on both devices separately. Similarly, it has to inform both the
master and slave device to transmit sync packets via the Sync Packet Transmit registers.
In summary, the following steps must be taken in order to synchronize input ports, either after reset and
initialization of the device, or when the control processor decides to resynchronize a link due to data errors on
the incoming packets. Even if on both the switch port and the remote device the same steps must be taken
they don’t have to be synchronous, but the global sequence of operation must be followed:
1. Disable the switch, by writing ‘0’b in register 0x‘03’ (it takes between 10 to 60ms to be effective), and
remote chip ports
2. Enable the switch, by writing ‘1’b in register 0x‘03’ (it takes between 10 to 60ms to be effective), and
remote chip ports
3. Disable DASL transmission. For the switch this imply writing a ‘1’b (it is bit map field) into the M3 picopro-
cessor address 0x‘400’ to disable ‘transmit sync enable’ internal line through command register 0x’1C’,
0x‘1D’ and 0x‘17’.
4. Check for valid connectivity of the receiver to a differential transmitter through the no signal register. This
is to ensure the integrity of the serial links.
5. Enable ‘Transmit Sync Packets’.
6. Enable DASL transmission. For the switch this imply writing a ‘0’b (it is bit map field) into the M3 picopro-
cessor address 0x‘400’ to validate ‘transmit sync enable’ internal line through command register 0x’1C’,
0x‘1D’ and 0x’17‘.
7. Write to the Sync Hunt register for the enabled ports to start synchronization.
8. Poll the Sync Status register to verify completion of synchronization after a Sync Time-Out period. If
some ports failed to synchronize, their Sync Status bits will be ‘0’b.
9. When synchronization has been achieved the local processor reports to the control processor that it is
ready for data transfer. Similarly the remote device does the same reporting.
10. Read CRC port ID register 0x‘0A’ and CRC error counter register to clear any CRC error indication that
might have been set up during synchronization period.
11. Upon reception of both reports, the control processor indicates to both ends of the full duplex link (switch
port and remote device) to stop transmitting Sync packets. Normal packet transfer (idle or data) on the
input ports can then be initiated.
12. As the link is now in data mode, the switch control has to poll the CRC Error registers and the No Signal
register to check for error free operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM32NPR101EPXCAC133 | Microprocessor |
| IBM37RGB524CF17A | Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | Video DAC with Color Palette (RAMDAC) |
| IBM39MPEGS420PBA18C | |
| IBM39MPEGS422PBA17C | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM32NPR101EPXCAC133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| IBM35CPC945C03C-2 | 制造商:IBM 功能描述: |
| IBM37RGB524CF17A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM39ENV422DLL00C | 制造商:IBM 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。