參數(shù)資料
型號： IBM32NPR100EXXCAB133
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 56/131頁
文件大?。?/td> 1679K
代理商： IBM32NPR100EXXCAB133
PRS28.4G
IBM Packet Routing Switch
Internal Registers
Page 56 of 131
prs28.03.fm
August 31, 2000
5.2 Application Register Definitions
The 32 Internal Application Registers provide the means to configure the device and report status informa-
tion.
All non-reserved bits in the Application Registers reset to zero during a flush reset operation, unless other-
wise specified. All reserved bits are set to ‘0’b. When a register containing reserved bits is written, ‘0’b must
be written to the reserved bit positions.
Table 19: Application Register List
Register Address
(dec)
Register Address
(hex)
Access
Functional Description
0
0
R/W
Mode Register
1
1
R/W
Configuration Register 0
2
2
R/W
Configuration Register 1
3
3
R/W
Port Enable Register
4
4
R/W
Output Queue Threshold Register
5
5
R/W
Shared Memory Threshold Register 0: priority 0 and 1
6
6
R/W
Shared Memory Threshold Register 1: priority 2 and 3
7
7
R/W
Mask Register
8
8
R/W
Synchronization Status and Hunt Register
9
9
R/W
Sync Packet Transmit Register
10
A
R
CRC Port ID Register
11
B
R
CRC Error Counter Register
12
C
R
NoSignal Register
13
D
R
Flow Control Violation Port ID Register
14
E
R
Miscellaneous Status Register
15
F
-
Reserved.
16
10
R
Output Queue Status Register 0
17
11
R
Output Queue Status Register 1
18
12
R
Output Queue Status Register 2
19
13
R
Output Queue Status Register 3
20
14
R/W
Table Pointer Register
21
15
R/W
Table Data Register
22
16
R/W
Memory Row Address Register
23
17
R/W
Command Register
24
18
R/W
Control Packet Destination Register
25
19
R/W
Bit Map Filter Register
26
1A
R
Yellow Idle Packet Received Register
27
1B
R/W
PLL Configuration Register
28
1C
R/W
Processor Address Register
29
1D
R/W
Processor Data Register
30
1E
R/W
BIST Data Register
31
1F
R/W
BIST Control Register
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