參數(shù)資料
型號： IBM32NPR100EXXCAB133
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 79/131頁
文件大?。?/td> 1679K
代理商： IBM32NPR100EXXCAB133
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Internal Registers
Page 79 of 131
5.2.23 Command Register
This register allows the software to initiate specific actions. Only one command can be set at a time. All
commands are interpreted as pulses, that is a command is only executed when the register is written to. This
register does not have to be cleared after the command has been executed.
Reserved
P
P
A
C
M
M
T
L
F
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Reset Value
0
OCM Address
17‘x’
Access Type
Read/Write
Bits
Description
0 - 6
Reserved
.
7
Processor Write
. Triggers a write command of the data in the Processor Data register to the Pico-Processor
address specified in the Processor Address register.
8
Processor Read
. Triggers a read command to the Pico-Processor address specified in the Processor Address
register. The result is returned in the Processor Data register.
9
ABIST Start
. Starts the ABIST process, which checks all RAMs. When the ABIST is running, the ABIST Active
bit of the Status register is active. And upon completion, the ABIST Pass/Fail status is reported in the Miscella-
neous Status Register. Note that the ABIST can only be run while the device is in Standby mode.
This command can only be triggered in Standby mode after Power-on Reset or Flush Reset.
10
Color Clear
. Clears the Idle Packet color state machine. After this command is initiated, Idle Packets of the
same color as the Expected Color are transmitted on a given output port when both following conditions are
satisfied: at least one packet of the expected color is received on all inputs, and the corresponding output
queue is empty. As long as these two conditions are not met, Idle Packets are transmitted with the opposite
color to the expected color.
11
Memory Row Write
. Triggers the writing of the Memory Row Data register to the shared memory row location
specified by the Memory Row Address register.
12
Memory Row Read
. Triggers the reading of the shared memory row location specified by the Memory Row
Address register and the loading of the data into the Memory Row Data register.
13
Transmit Control Packet
. Triggers the transmission of the Control Packet, located in shared memory address
0 (and 1 if not in internal and external speed expansion), on all the ports specified in the Control Packet Desti-
nation register. The Control Packet Transmitted interrupt is generated once the packet has been transmitted by
all the specified ports.
14
Load Next Control Packet Address
. Loads the address at the top of the control packet queue into the Mem-
ory Row Address Register. Note that the read address stays at the top of the control packet queue.
15
Free Control Packet Address
. Frees the address at the top of the control packet queue. The following
address moves to the top.
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