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| 型號(hào)： | IBM32NPR100EXXCAB133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 44/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR100EXXCAB133 |
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PRS28.4G
IBM Packet Routing Switch
Functional Description
Page 44 of 131
prs28.03.fm
August 31, 2000
3.13.2 Control Packet Transmission
The local processor has write access to the entire packet memory. The memory locations with address 0, 1
and 256 are special (see table below). The contents of these rows can be transmitted upon command from
the local processor.
3.14 Speed Expansion
The purpose of speed expansion is to increase the physical port speed of a switch. Two methods, external
speed expansion and internal speed expansion, are supported. Internal and external speed expansion may
not be combined together.
3.14.1 External Speed Expansion
Two devices, one master and one slave, can be used in external speed expansion mode. The master device
performs all the address handling. It maintains the output queues and the address manager. These compo-
nents are idle in the slave device. Packet addresses, used by the inputs, are sent from the master device to
the slave device on a special input address bus. The timing in a master device enables master inputs to
receive new addresses at the same time as all the slave inputs.
Packet addresses used by the outputs are sent in a similar fashion from the master device to the slave
device. The timing in the master device enables a master output to receive a new retrieve address at the
same time as the slave output. A master output and the corresponding slave output always start the transmis-
sion of a packet simultaneously.
When two devices are in external speed expansion, ports of the same number are grouped together.
3.14.2 Internal Speed Expansion
It is also possible to connect two ports on the same device together in speed expansion. This allows for a
1.77 Gb/s per port 16x16 switch or a 3.54 Gb/s 8x8 switch. The table below shows which inputs and outputs
are combined.
Table 11: Shared Memory Reserved Address for Control Packets
External Speed
Expansion
Internal Speed
Expansion
Packet Size (No. of Bytes)
Shared Memory Reserved Address
0
0
64 to 80
0 and 1
0
1
64 to 80
0 and 256
1
0
64 to 80
0
1
0
128 to 160
0 and 1
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