- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360706 > IBM32NPR100EXXCAB133 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | IBM32NPR100EXXCAB133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 90/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR100EXXCAB133 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁當(dāng)前第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁
PRS28.4G
IBM Packet Routing Switch
Reset, Initialization, and Operation
Page 90 of 131
prs28.03.fm
August 31, 2000
Whenever a Flush Reset sequence is triggered, the following steps must occur before normal operation can
take place:
1. After completion of the Flush Reset sequence, the chip core logic is in Standby mode (that is, the applica-
tion registers can be programmed) but the output pins stay tri-stated and the data presented on input pins
is ignored, except for the OCM island pins. Even though most registers can be programmed during nor-
mal operation, the following registers must be programmed
during standby only
:
Configuration Register 0
Configuration Register 1
Mode Register with M3_Reset = 1‘b’ and ColorForce = 1‘b’.
2.
Standby Mode must be exited
by setting bit 15 of the Mode Register to 0‘b’.
3. The Processor Instruction Memory has to be programmed, while keeping the Mode Register M3_Reset
at ‘1’b. After the Processor Instruction Memory is programmed, the M3_Reset bit is released.
4. Depending on the system configuration, the Bit Map Filter register and Look-Up Table are also pro-
grammed.
5. The Port Enable Register can be programmed, by following the sequence described below.
6. An OCM OCD_ENABLE command must be issued. This command enables the functional primary output
drivers to drive the data busses. This command also allows interrupts to occur. No interrupts will occur on
the EMB bus until the OCDs are enabled with the OCM OCD_ENABLE command.
Standby mode should not be entered from normal operation mode. Programming the Standby bit to ‘1’b from
‘0’b while in normal operation mode will result in unpredictable behavior. Standby mode can only be entered
after Power-On-Reset, Soft Reset, or BIST.
During operation, all registers can be programmed except for the Configuration registers 0 and 1. Program-
ming these two registers while in normal operation mode (Standby bit at ‘0’b) could result in unpredictable
behavior. The Processor Instruction Memory can be programmed at all times during normal operation with
the provision that the M3_Reset bit on the Mode register is set to ‘1’b during programming.
6.4 DASL Initialization and Operation
Once the PRS28.4G has been fully configured and before actual data traffic can take place between any
PRS28.4G and the adapter(s), the DASL interfaces must be initialized to provide bit phase alignment and
packet alignment at the data receivers in both directions.
Note:
DASL initialization involves communication between the IBM3209K4060 and the device connected to
a specific PRS28.4G port, which is referred to as the remote device (located in the adapter).
The port synchronization is under the overall control of the using system Control Processor which coordinates
the operation between the switch core and the adapters. For PRS28.4G switch elements, this synchroniza-
tion is handled by the local processor (running the switch control microcode), connected to the OCM inter-
face, after initialization or after error detection. But it can also be performed directly through interface lines
between the switch control and the port adapter.
The registers of interest in this case are:
1. Port enable register 0x’03‘
2. No signal register 0x’0C‘
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM32NPR101EPXCAC133 | Microprocessor |
| IBM37RGB524CF17A | Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | Video DAC with Color Palette (RAMDAC) |
| IBM39MPEGS420PBA18C | |
| IBM39MPEGS422PBA17C | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM32NPR101EPXCAC133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| IBM35CPC945C03C-2 | 制造商:IBM 功能描述: |
| IBM37RGB524CF17A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM39ENV422DLL00C | 制造商:IBM 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。