參數(shù)資料
型號(hào)： IBM32NPR100EXXCAB133
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 28/131頁
文件大小： 1679K
代理商： IBM32NPR100EXXCAB133
PRS28.4G
IBM Packet Routing Switch
Functional Description
Page 28 of 131
prs28.03.fm
August 31, 2000
3.1.2.2 Idle Packets
The format of an Idle Packet without speed expansion (normal mode) is identical to data packet formats,
except that an Idle Packet contains two trailer-bytes in the last word of the packet.
Idle Packet format with speed expansion is similar to the data packet format for a 3.54 Gb/s port, except for
the trailer-bytes at the end of the packet.
Like Data Packets, Idle Packets also carry color information. However, in this case the color information is for
signaling (such as liveness messages, or to identify link synchronization packets, called Sync packets), in
addition to switchover support.
The payload bytes of nonsync Idle Packets - shown as ‘D’ in the above two figures - are not processed and
are therefore irrelevant. However, in order to allow for dynamic phase alignment for the link interface receiver,
6 payload bytes are ‘CC’. All bytes of a non-sync Idle-packet LU transmitted by the PRS28.4G have the value
‘00’, with the following exceptions:
Bytes 6 to 11 are all 0x‘CC’.
Byte 5 of a slave LU is 0x‘07’.
The last byte contains the trailer CRC.
For a master LU, the header is defined according to the following sections.
3.1.2.3 Sync Packet
Sync packets are special types of Idle Packets, which allow link synchronization by providing bit transition
and packet delineation.
In accordance with the above definition of an Idle Packet, a Sync packet LU has all bytes equal to ‘CC',
except for the last byte, the trailer CRC byte, which is ‘33'.
The bit organization by the physical interface provides on a given differential pair, a sequence of ‘A', followed
by a ‘5'. This bit sequence provides the necessary bit transition while the ‘A to 5' transition allows for packet
delineation.
Figure 7: Idle Packet Format
H0
H1
H2
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
T
D
D
D
T
W0
W1
W2
W3
W4
W5
W6
W(L-1)
D
D
. . .
. . .
. . .
Master LU
Slave LU
16 Bits
Normal Mode
H0
H1
H2
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
T
D
D
D
T
W0
W1
W2
W3
W4
W5
W6
W(L-1)
D
D
. . .
. . .
. . .
Master LU
Slave LU
16 Bits
Master Port
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
T
D
D
D
T
D
D
. . .
. . .
Slave LU
Slave LU
16 Bits
Slave Port
D
D
D
Speed Expansion Mode
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