
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Programming Interface and Internal Registers
Page 53 of 131
6. A second Flush Reset occurs.
7. The BIST ACTIVE bit in the Status Register is deasserted (‘0’b).
During BIST the OCM READ STATUS command should be used to read the Status Register. If the BIST or
Reset active bit is active (‘1’b), the other status bits as well as the parity bit are invalid and should be ignored.
Once BIST is complete the BIST or Reset Active bit will be inactive (‘0’b). An interrupt will not occur. There-
fore, the BIST or Reset active bit must be polled using the OCM READ STATUS command to determine
when BIST is complete. While BIST is running, the OCM READ STATUS command will not clear the Status
Register. This prevents the BIST signature from being corrupted.
After BIST is completed, the MISR value can be accessed via the Application Registers.
The User BIST execution time is 30040 ns + (BIST Cycle Count value) X 50020 ns (for clock cycle of 10 ns).
The User Defined BIST was run against the final chip net list in simulation. The initial and final register values
were:
Table 17: Simulated BIST Signatures
Initial BCCOUNT
Initial PRPG
Initial MISR
Final PRPG
Final MISR (signature)
Default Bist
0x”F880 CFAD”
0x”3215 7C0A”
User Bist: 30
0x”122 3344”
0x”556 67788”
0x”1A98 29ED”
0x”F49F 1415”
User Bist: 100
0x”5555 5555”
0x”CCCC CCCC”
0x”F8FE DD72”
0x”24A2 3D63”