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| 型號： | IBM32NPR100EXXCAB133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 48/131頁 |
| 文件大小： | 1679K |
| 代理商： | IBM32NPR100EXXCAB133 |
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PRS28.4G
IBM Packet Routing Switch
Programming Interface and Internal Registers
Page 48 of 131
prs28.03.fm
August 31, 2000
011
READ
REGISTER
16-bits of data from the Application Register specified by the ‘ADDR’ field of the instruction are
loaded into the response register. The response to this command is the data read from the
specified Application Register.
100
EVENT
This instruction provides control of four functions:
Start of the internal clock logic.
Initialization of Built In Self Test (BIST).
Bypass of the internal scan chain when the a scan operation is performed via the OCM.
Control of clock (stop, run).
The response to this instruction is ‘DATA’ field.
‘ADDR’ Field Bit Function
0 to 4: Reserved.
‘DATA’ Field Bit Function
0 to 2: Reserved
3:
Start BIST
: A ‘1’b in this position causes the BIST to start. Returns programmed value in
response. If this bit is set to ‘1’b all other bits within this command are ignored. When this bit is
set, bit 4 also has to be programmed.
4:
Scan/BIST Select
:
* (With bit 3 set to ‘0’b.) When set to ‘1’b the internal scan string receives scan data. Scan
mode must be entered immediately after this command. When set to ‘0’b the scan data
passes through the one bit scan bypass register. Returns programmed value in response.
* (With bit 3 set to ‘1’b.) When set to ‘0’b for Default BIST. When set to ‘1’b runs the User Con-
trolled BIST.
5:
Clock Start
: When this bit is set to ‘1’b, the internal clock logic is enabled.
When using the internal PLL, the PLL Register must be programmed before sending the Clock
Start Event, in order to enable the PLL. Once the Clock Start Event is sent, the PLL Reset is
released, and the 400 MHz logic reset is triggered, followed by flush reset of the entire core
logic. See the Chapter on Reset for details.
When using an external PLL, the PLL Register should not be programmed, and the Clock
Start Event should only be sent once the external PLL has locked. Once the Clock Start Event
is sent, the 400 MHz logic reset is triggered, followed by flush reset of the entire core logic.
See the Chapter on Reset for details.
Returns programmed value in response.
6: CLKCTL1 (Clk control bit 0): Reserved - always set to ‘0’b.
7: CLKCTL2 (Clk control bit 1): When set to ‘1’b, causes the internal 100 MHz clock to stop.
When set to ‘0’b, allows the internal 100 Mhz to run freely. Returns programmed value in
response.
8 to15: Reserved.
101
RESET
This command initiates a Flush Reset of the entire core logic, not including the OCM, Clock
generation, Reset and BIST island. The values in the ‘ADDR’ and ‘DATA’ fields are ignored.
This command does not have a “response”. It must be followed by an ‘ECHO’ command.
110
READ
STATUS
This command allows the reading of the internal Status Register. The Status Register content
is loaded into the response register when SELECT is deactivated. The response to this com-
mand is the current contents of the Status Register. The Status Register is cleared after its
contents are loaded into the response register.
The values in the ‘ADDR’ and ‘DATA’ fields are ignored.
111
OCD ENABLE/
DISABLE
This command is used to enable and disable the functional drivers. The enable signal gener-
ated by this command is logically ANDed with all of the functional driver enables except
B_CLK_OUT, C_CLK_OUT, PLL_LOCK, PLL_TESTOUT, SCAN_OUT, TDO.
The ‘ADDR’ field bits are reserved.
All of the ‘DATA’ field bits are reserved except ‘DATA’ bit 15. This bit is the enable bit. When
set to ‘1’b the PRS28.4G drivers are enabled, and when set to ‘0’b the PRS28.4G drivers are
set to a high impedance state. The ‘DATA’ field is returned in the response.
Table 13: OCM Instruction Set Definitions
(Page 2 of 2)
Op Code
Command
Command Description
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