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| 型號(hào)： | IBM32NPR100EXXCAB133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 55/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR100EXXCAB133 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Internal Registers
Page 55 of 131
A “Y” in the maskable column indicates that a particular event can be masked out by setting the appropriate
bit in the Mask Register. When the mask bit is enabled, these events will set the appropriate bit in the status
register but will not result in the activation of the EMB_SIGNAL_OUT (if enabled), which is used as an inter-
rupt to the microprocessor.
Bit 15 is a status bit and does not reflect the occurrence of an event. It is not maskable.
For an interrupt to occur (EMB_SIGNAL_OUT set to ‘0’b), the status bit must not be masked (if maskable)
and the EMB_SIGNAL_OUT primary output must be enabled via the Mode Register. After a power on reset
occurs, none of the mask bits are set, and the EMB_SIGNAL_OUT primary output is disabled. It is enabled
after an OCM OCD Enable command.
10
Y
Processor Error
: Interrupt generated when the local processor initiates a new command or opera-
tion while the chip internal logic is not ready. This interrupt can be generated in four different situa-
tions:
Row Read Error. Generated when the local processor has issued a Memory Row Read com-
mand, and tries to actually read the Memory Row Register when the new row value is not avail-
able yet.
Row Write Error. Generated when the local processor tries to write to the Memory Row Register
just after a Memory Row Write command, and the data in the row register has not be written to
memory yet. The Memory Row register is not overwritten by the new value when this interrupt is
generated.
Transmit Error. Generated when the local processor initiates a Control Packet Transmit com-
mand while Memory Row Register has not been written to the shared memory yet.
Address Write Error. Generated when the Memory Row Address register is written to after a
Memory Row Write command, and the memory data has not been written yet. The Address
value is not overwritten by the new value when this interrupt is generated.
11
Y
Out of Synchronization Interrupt
, due to 8 CRC errors received in row or 8 parity bit errors received
in row.
12
Y
Signal Detect Interrupt
. Interrupt generated whenever a bit in the Signal Detect register changes,
either from high to low, or from low to high.
13
Y
Flow Control Violation
. Interrupt generated whenever a packet is received on an input port while no
store addresses are available. Also, if the Flow Control Check Enable is set in the Mode Register, this
interrupt is generated when a packet is destined to outputs for which no grant has been given in the
past 8 packet cycles (see description of the Flow Control Check Enable bit). The ports are identified
via the Flow Control Violation Port ID register.
14
Y
M3 Interrupt
: When set to ‘1’b, it indicates that the internal picoprocessor (M3) has generated an
interrupt.
15
N
BIST / ABIST / Reset Active
: Set to ‘1’b when either BIST, ABIST or Flush Reset is executing. All
other bits as well as the OCM parity bit within this register are invalid when this bit is set to ‘1’b. This
bit automatically resets itself when BIST, ABIST, or Flush Reset is completed. This bit does not gen-
erate an interrupt.
Table 18: Status Register Bit Definitions
(Page 2 of 2)
Bits
Maskable
Description
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