參數(shù)資料
型號： IBM32NPR100EXXCAB133
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 43/131頁
文件大?。?/td> 1679K
代理商： IBM32NPR100EXXCAB133
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Functional Description
Page 43 of 131
3.11 Port Disabling
A port (meaning an input port and the corresponding output port) can only be disabled by programming the
Port Enable register.
The output queues of disabled ports are flushed (slow flush) at the speed at which Data Packets are trans-
mitted, regardless of the SND_GRANT of those outputs.
3.12 Address Manager and Address Corruption
The address manager controls packet addresses by maintaining a pool of free addresses and occupancy
counters for each address. It provides the input controllers with addresses from the free address pool. When
an address is used, the occupancy counters are initialized to the number of destinations of the corresponding
packet. Each time a packet is transmitted, the occupancy counter of its address is decremented by one.
Finally, when the counter reaches zero, the address is returned to the free address pool.
Since addresses are continuously used as packets are being received and transmitted, it is important to
detect address corruption scenarios. Address corruption can lead not only to corruption of packets, but also to
a loss of available addresses, which can decrease performance.
Therefore, two error detection mechanisms are in place to detect corruption:
Each output queue is protected by parity. When an address is written to an output queue, parity is gener-
ated and stored with the address, and it is checked upon reading this location.
The address manager detects the following error scenarios:
- A counter is initialized to a value, while it is not zero,
- An address is freed by an output controller when its counter is zero.
Each of these errors sets the Address Corruption interrupt and, if not masked, the main interrupt is asserted.
3.13 Control Packets
It is possible to address a local processor attached to an PRS28.4G by means of Control Packets. A Control
Packet is like a normal Data Packet, except that its memory addresses are stored in a special Control Packet
queue.
3.13.1 Control Packet Reception
When a Control Packet is received, it is enqueued into the Control Packet queue if room is available. The
Control Packet queue has 16 locations. This allows fairness among all inputs. Indeed, each input can receive
a Control Packet at the same time and all packets can be processed.
If the queue is full when a Control Packet arrives, it is discarded. When a Control Packet is accepted, a
Control Packet Received interrupt is generated and, if not masked, the main interrupt is asserted. The local
processor can then access the Control Packets via the Table Pointer and Data registers and the Memory
Address register. The complete Control Packet access is described in
Control Packet Reception and Trans-
mission
on page 92.
Note:
The reference of the input port which received the Control Packet, is inserted in the packet.
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