- 您現在的位置：買賣IC網 > PDF目錄370785 > HYB25R144180C (SIEMENS AG) 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) PDF資料下載
參數資料
| 型號： | HYB25R144180C |
| 廠商： | SIEMENS AG |
| 英文描述： | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| 中文描述： | 144兆位的直接的RDRAM（144兆直接的RDRAM） |
| 文件頁數： | 79/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25R144180C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
Data Book
79
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Figure 58
also shows the combinational path connecting SIO0 to SIO1 and the path connecting
SIO1 to SIO0 (read data only). The
t
PROP1
parameter specified this propagation delay. The rise and
fall times of SIO0 and SIO1 inputs must be
t
DR1
and
t
DF1
, measured at the 20% and 80% levels. The
rise and fall times of SIO0 and SIO1 outputs are
t
QR1
and
t
QF1
, measured at the 20% and 80% levels.
RSL - Domain Crossing Window
When read data is returned by the RDRAM, information must cross from the receive clock domain
(CFM) to the transmit clock domain (CTM). The
t
TR
parameter permits the CFM to CTM phase to
vary through an entire cycle; i.e. there is no restriction on the alignment of these two clocks. A
second parameter
t
DCW
is needed in order to describe how the delay between a RD command
packet and read data packet varies as a function of the
t
TR
value.
Figure 59
shows this timing for five distinct values of
t
TR
. Case A (
t
TR
= 0) is what has been used
throughout this document. The delay between the RD command and read data is
t
CAC
. As
t
TR
varies
from zero to
t
CYCLE
(cases A through E), the command to data delay is (
t
CAC
–
t
TR
). When the
t
TR
value is in the range 0 to
t
DCW,MAX
, the command to data delay can also be (
t
CAC
–
t
TR
–
t
CYCLE
). This
is shown as cases A’ and B’ (the gray packets). Similarly, when the t
TR
value is in the range
(
t
CYCLE
+
t
DCW,MIN
) to
t
CYCLE
, the command to data delay can also be (
t
CAC
–
t
TR
+
t
CYCLE
). This is
shown as cases D’ and E’ (the gray packets). The RDRAM will work reliably with either the white or
gray packet timing. The delay value is selected at initialization, and remains fixed thereafter.
相關PDF資料 |
PDF描述 |
|---|---|
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-60 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-60 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ | RES 10K-OHM 1% 0.063W 200PPM THICK-FILM SMD-0402 5K/REEL-7IN-PA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
發(fā)布緊急采購，3分鐘左右您將得到回復。