參數(shù)資料
型號(hào)： HYB25R144180C
廠商： SIEMENS AG
英文描述： 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述： 144兆位的直接的RDRAM（144兆直接的RDRAM）
文件頁(yè)數(shù)： 31/93頁(yè)
文件大小： 919K
代理商： HYB25R144180C
Data Book
31
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Figure 15
Read Transaction Example
Write Transaction - Example
Figure 16
shows an example of a write transaction. It begins by activating a bank with an ACT a0
command in an ROWA packet. A time
t
RCD
–
t
RTR
later a WR a1 command is issued in a COLC
packet (note that the
t
RCD
interval is measured to the end of the COLC packet with the first retire
command). Note that the ACT command includes the device, bank, and row address (abbreviated
as a0) while the WR command includes device, bank, and column address (abbreviated as a1). A
time
t
CWD
after the WR command the write data dualoct D(a1) is issued. Note that the packets on the
ROW and COL pins use the end of the packet as a timing reference point, while the packets on the
DQA/DQB pins use the beginning of the packet as a timing reference point.
A time
t
CC
after the first COLC packet on the COL pins a second COLC packet is issued. It contains
a WR a2 command. The a2 address has the same device and bank address as the a1 address (and
a0 address), but a different column address. A time
t
CWD
after the second WR command a second
write data dualoct D(a2) is issued.
A time
t
RTR
after each WR command an optional COLM packet MSK (a1) is issued, and at the same
time a COLC packet is issued causing the write buffer to automatically retire. See
Figure 17
for
more detail on the write/retire mechanism. If a COLM packet is not used, all data bytes are
unconditionally written. If the COLC packet which causes the write buffer to retire is delayed, then
the COLM packet (if used) must also be delayed.
Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank
to precharge so that a different row may be activated in a subsequent transaction or so that an
adjacent bank may be activated. The a3 address includes the same device and bank address as the
a0, a1, and a2 addresses. The PRER command must occur a time
t
RAS
or more after the original
a1 = {Da, Ba, Ca1}
Transaction b: XX
Transaction a: RD
DQA8...0
DQB8...0
t
b0 = {Da, Ba, Rb}
a0 = {Da, Ba, Ra}
RCD
t
t
CAC
CC
Q (a1)
t
CAC
t
RDP
a3 = {Da, Ba}
a2 = {Da, Ba, Ca2}
Q (a2)
SPT04219
T24
ROW2...
ROW0
CTM/CFM
COL4...COL0
ACT a0
T2
T0
T1
T3
T4
RD a2
RD a1
RAS
t
t
RC
T14
T7
T5
T6
T8
T9
T10 T11
T13
T12
T19
T15 T16
T18
T17
T20 T21
T23
T22
ACT b0
PRER a3
T34
T29
T25 T26 T27 T28
T30 T31 T32 T33
T39
T36
T35
T37 T38
T41
T40
T42 T43
T46
T45
T44
T47
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