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參數資料
| 型號： | HYB25R144180C |
| 廠商： | SIEMENS AG |
| 英文描述： | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| 中文描述： | 144兆位的直接的RDRAM（144兆直接的RDRAM） |
| 文件頁數： | 14/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB25R144180C |
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Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
14
2.00
DQ Packet Timing
Figure 4
shows the timing relationship of COLC packets with D and Q data packets. This document
uses a specific convention for measuring time intervals between packets: all packets on the ROW
and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a
reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet
as a reference point.
An RD or RDA command will transmit a dualoct of read data Q a time
t
CAC
later. This time includes
one to five cycles of round-trip propagation delay on the Channel. The
t
CAC
parameter may be
programmed to a one of a range of values (7, 8, 9, 10, 11, or 12
t
CYCLE
). The value chosen depends
upon the number of RDRAM devices on the Channel and the RDRAM timing bin. See
Figure 39
for
more information.
A WR or WRA command will receive a dualoct of write data D a time
t
CWD
later. This time does not
need to include the round-trip propagation time of the Channel since the COLC and D packets are
traveling in the same direction.
When a Q packet follows a D packet (shown in the left half of the figure), a gap (
t
CAC
–
t
CWD
) will
automatically appear between them because the
t
CWD
value is always less than the
t
CAC
value.
There will be no gap between the two COLC packets with the WR and RD commands which
schedule the D and Q packets.
When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between
them because the
t
CWD
value is less than the
t
CAC
value. However, a gap of
t
CAC
–
t
CWD
or greater
must be inserted between the COLC packets with the RD WR commands by the controller so the
Q and D packets do not overlap.
Figure 4
Read (Q) and Write (D) Data Packet - Timing for
t
CAC
= 7, 8, 9, 10, 11, or 12
t
CYCLE
DQA8...0
DQB8...0
Q (y1)
CAC
t
Q (b1)
SPA04208
CAC
t
Q (c1)
D (d1)
T25
T5
RD b1
This gap on the DQA/DQB pins appears automatically
ROW0
ROW2...
COL4...COL0
WR a1
CTM/CFM
T0
T1
T2
T3
T4
-
CWD
t
t
CAC
t
CWD
T15
T10
T6
T7
T8
T9
T11 T12 T13 T14
T20
T17
T16
T18 T19
T22
T21
This gap on the COL pins must be inserted by the controller
RD c1
CAC
t
t
CWD
-
CWD
t
WR d1
T35
T30
T27
T26
T28 T29
T32
T31
T33 T34
T37
T36
T38 T39
T42
T41
T40
T43 T44
T47
T46
T45
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