參數(shù)資料
型號: HYB25R144180C
廠商: SIEMENS AG
英文描述: 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述: 144兆位的直接的RDRAM(144兆直接的RDRAM)
文件頁數(shù): 73/93頁
文件大?。?/td> 919K
代理商: HYB25R144180C
Data Book
73
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Figure 53
RSL Timing - Clock Signals
The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB,
ROW and COL outputs. Most timing is measured relative to the points where they cross. The
t
CYCLE
parameter is measured from the falling CFM edge to the falling CFM edge. The
t
CL
and
t
CH
parameters are measured from falling to rising and rising to falling edges of CFM. The
t
CR
and
t
CF
rise- and fall-time parameters are measured at the 20% and 80% points.
The
t
TR
parameter specifies the phase difference that may be tolerated with respect to the CTM and
CFM differential clock inputs (the CTM pair is always earlier).
SPT04239
20%
V
CIL
CIH
80%
50%
V
CFMN
CFM
TR
t
CR
V
X-
t
CM
V
X+
V
t
CR
t
CF
CF
t
CL
t
CH
t
CYCLE
t
CTM
80%
50%
CIH
CIL
20%
V
V
CTMN
CL
t
CYCLE
t
X-
V
CR
CR
t
CF
CH
t
X+
V
V
CM
t
CF
t
t
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