參數(shù)資料
型號(hào)： HYB25R144180C
廠商： SIEMENS AG
英文描述： 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述： 144兆位的直接的RDRAM（144兆直接的RDRAM）
文件頁(yè)數(shù)： 47/93頁(yè)
文件大?。?/td> 919K
代理商： HYB25R144180C
Data Book
47
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
024
16
CNFGB
BYT
read-only, 1 bit
Byte. Specifies an 8-bit or 9-bit byte size.
DEVTYP read-only, 3 bit
Device type. Device can be RDRAM or some other
device category.
SPT
read-only, 1 bit
Split-core. Each core half is an individual dependent
core.
CORG
read-only, 6 bit
Core organization. Bank, row, column address field
sizes.
SVER
read-only, 6 bit
Stepping version. Mask version number.
040
16
041
16
DEVID
DEVID
read-write, 5 bits
Device ID. Device address for memory read/write.
REFB
REFB
read-write, 4 bits
Refresh bank. Next bank to be refreshed by
self-refresh.
042
16
REFR
REFR
read-write, 9 bits
Refresh row. Next row to be refreshed by REFA, self-
refresh.
043
16
CCA
CCA
read-write, 7 bits
Current control A. Controls
I
OL
output current for DQA.
Asymmetry control. Controls asymmetry of
V
OL
/
V
OH
swing for DQA.
ASYMA
read-write, 2 bits
044
16
CCB
CCB
read-write, 7 bits
Current control B. Controls I
OL
output current for DQB.
Asymmetry control. Controls asymmetry of
V
OL
/
V
OH
swing for DQB.
ASYMB
read-write, 2 bits
045
16
NAPX
NAPXA
read-write, 5 bits
NAP exit. Specifies length of NAP exit phase A.
NAPX
read-write, 5 bits
NAP exit. Specifies length of NAP exit phase
A + phase B.
DQS
read-write, 1 bits
DQ select. Selects CMD framing for NAP/PDN exit.
046
16
047
16
PDNXA
PDNXA
read-write, 13 bits
PDN exit. Specifies length of PDN exit phase A.
PDNX
PDNX
read-write, 13 bits
PDN exit. Specifies length of PDN exit phase
A + phase B.
048
16
TPARM
TCAS
read-write, 2 bits
t
core parameter. Determines
t
OFFP
data sheet
parameter.
TCLS
read-write, 2 bits
t
core parameter. Determines
t
CAC
and
t
OFFP
parameters.
TCDLY0
read-write, 3 bits
t
core parameter. Programmable delay for read
data.
049
16
TFRM
TFRM
read-write, 4 bits
t
core parameter. Determines ROW-COL packet
framing interval.
04a
16
TCDLY1
TCDLY1
read-write, 3 bits
t
CDLY1-C
core parameter. Programmable delay for read
data.
04c
16
TCYCLE
TCYCLE
read-write, 14 bits
t
data sheet parameter. Specifies cycle time in
64 ps units.
Table 17
Control Register Summary
(cont’d)
SA11…SA0
Register
Field
read-write/
read-only
Description
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