參數(shù)資料
型號(hào): HYB25R144180C
廠商: SIEMENS AG
英文描述: 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述: 144兆位的直接的RDRAM(144兆直接的RDRAM)
文件頁數(shù): 74/93頁
文件大?。?/td> 919K
代理商: HYB25R144180C
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
74
2.00
RSL - Receive Timing
Figure 54
is a timing diagram which shows the detailed requirements for the RSL input signals on
the Channel.
The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a
Direct RAC on the Channel. Each signal is sampled twice per
t
CYCLE
interval. The set/hold window
of the sample points is
t
S
/
t
H.
The sample points are centered at the 0% and 50% points of a cycle,
measured relative to the crossing points of the falling CFM clock edge. The set and hold parameters
are measured at the
V
REF
voltage point of the input transition.
The
t
DR
and
t
DF
rise- and fall-time parameters are measured at the 20% and 80% points of the input
transition.
Figure 54
RSL Timing - Data Signals for Receive
SPT04240
20%
V
DIL
DIH
80%
V
DQB
ROW
COL
DR
t
t
S
CFM
80%
50%
CIH
CIL
20%
V
V
CFMN
X-
V
X+
V
V
CM
DQA
t
DF
t
H
t
S
H
t
t
CYCLE
0.5 x
Even
Odd
REF
V
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