參數(shù)資料
型號: HYB25R144180C
廠商: SIEMENS AG
英文描述: 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述: 144兆位的直接的RDRAM(144兆直接的RDRAM)
文件頁數(shù): 77/93頁
文件大?。?/td> 919K
代理商: HYB25R144180C
Data Book
77
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
The SCK clock is also used for sampling data on RSL inputs in one situation.
Figure 48
shows the
PDN and NAP exit sequences. If the PSX field of the INIT register is one (see
Figure 27
), then the
PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform
the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences
are directed; i.e. only one RDRAM that is in PDN or NAP will perform the exit sequence.
The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window
t
S3
/
t
H3
around
the rising edge of SCK. This is shown in
Figure 57
. The SCK timing point is measured at the 50%
level, and the DQA[5:0] bus signals are measured at the
V
REF
level.
Figure 57
CMOS Timing - Device Address for NAP or PDN Exit
CMOS - Transmit Timing
Figure 58
is a timing diagram which shows the detailed requirements for the CMOS output signals.
The SIO0 signal is driven once per
t
CYCLE1
interval on the falling edge. The clock-to-output window
is
t
Q1,MIN
/
t
Q1,MAX.
The SCK and SIO0 timing points are measured at the 50% level. The rise and fall
times of SIO0 are
t
QR1
and
t
QF1
, measured at the 20% and 80% levels.
SPT04243
20%
V
DIL
DIH
80%
V
DQA(5:0)
SCK
80%
50%
IH, CMOS
V
IL, CMOS
V
20%
t
H3
t
S3
PDEV
V
REF
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