參數(shù)資料
型號： HYB25R144180C
廠商： SIEMENS AG
英文描述： 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述： 144兆位的直接的RDRAM（144兆直接的RDRAM）
文件頁數(shù)： 58/93頁
文件大?。?/td> 919K
代理商： HYB25R144180C
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
58
2.00
Figure 44
TCYCLE Register
Power State Management
Table 18
summarizes the power states available to a Direct RDRAM. In general, the lowest power
states have the longest operational latencies. For example, the relative power levels of PDN state
and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have
a ratio of about 250:1.
PDN state is the lowest power state available. The information in the RDRAM core is usually
maintained with self-refresh; an internal timer automatically refreshes all rows of all banks. PDN has
a relatively long exit latency because the TCLK/RCLK block must resynchronize itself to the external
clock signal.
NAP state is another low-power state in which either self-refresh or REFA-refresh are used to
maintain the core. See “Refresh” on page 64 for a description of the two refresh mechanisms. NAP
has a shorter exit latency than PDN because the TCLK/RCLK block maintains its synchronization
state relative to the external clock signal at the time of NAP entry. This imposes a limit (
t
NLIMIT
) on
how long an RDRAM may remain in NAP state before briefly returning to STBY or ATTN to update
this synchronization state.
Table 18
Power State Summary
Power
State
Description
Blocks Consuming
Power
Power
State
Description
Blocks Consuming
Power
PDN
Powerdown state.
Self-refresh
NAP
Nap state. Similar to
PDN except lower
wake-up latency.
Self-refresh or
REFA-refresh
TCLK/RCLK-Nap
STBY
Standby state.
Ready for ROW
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
ATTN
Attention state.
Ready for ROW and
COL packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
ATTNR Attention read state.
Ready for ROW and
COL packets.
Sending Q (read
data) packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ mux transmitter
Core power
ATTNW Attention write state.
Ready for ROW and
COL packets.
Ready for D (write
data) packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ demux receiver
Core power
11
14
0
0
15
13 12
Address: 04C
16
Control Register: TCYCLE
10 9
TCYCLE13...TCYCLE0
7
8
6
3
5
4
2
1
0
Read/write register.
Reset value is undefined
TCYCLE13...0 - Specifies the value of the
t
CYCLE
datasheet parameter in 64 ps units. For the
t
CYCLE, MIN
of 2.5 ns (2500 ps), this field should be
written with the value “00027 16 ” (39 * 64 ps).
SPD04290
相關(guān)PDF資料
PDF描述
HYB3116160BST-70 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
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HYB3116160BSJ-70 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BST-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
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