參數(shù)資料
型號： HYB25R144180C
廠商： SIEMENS AG
英文描述： 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述： 144兆位的直接的RDRAM（144兆直接的RDRAM）
文件頁數(shù)： 46/93頁
文件大?。?/td> 919K
代理商： HYB25R144180C
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
46
2.00
transaction should be made to each RDRAM in order to ensure that the output pipeline stages have
been cleared.
Initialization Note [4]:
The SETF command (in the serial SRQ packet) should only be issued once during the Initialization
process, as should the SETR and CLRR commands.
Initialization Note [5]:
The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in
an indeterminate state.
Control Register Summary
Table 17
summarizes the RDRAM control registers. Detail is provided for each control register in
Figure 27
through
Figure 43
. Read-only bits which are shaded gray are unused and return zero.
Read-write bits which are shaded gray are reserved and should always be written with zero. The
RIMM SPD Application Note (DL-0054) describes additional read-only configuration registers which
are present on Direct RIMMs.
The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR
operation. This is indicated in the text accompanying each register diagram.
Table 17
Control Register Summary
SA11…SA0
Register
Field
read-write/
read-only
Description
021
16
INIT
SDEVID
read-write, 6 bits
Serial device ID. Device address for control register
read/write.
PSX
read-write, 1 bit
Power select exit. PDN/NAP exit with device addr on
DQA5 … 0.
SRP
read-write, 1 bit
SIO repeater. Used to initialize RDRAM.
NSR
read-write, 1 bit
NAP self-refresh. Enables self-refresh in NAP mode.
PSR
read-write, 1 bit
PDN self-refresh. Enables self-refresh in PDN mode.
LSR
read-write, 1 bit
Low power self-refresh. Enables low power
self-refresh.
TEN
read-write, 1 bit
Temperature sensing enable.
TSQ
read-write, 1 bit
Temperature sensing output.
DIS
read-write, 1 bit
RDRAM disable.
022
16
023
16
TEST34
TEST34
read-write, 16 bits
Test register. Do not read or write after SIO reset.
CNFGA
REFBIT
read-only, 3 bit
Refresh bank bits. Used for multi-bank refresh.
DBL
read-only, 1 bit
Double. Specifies doubled-bank architecture
MVER
read-only, 6 bit
Manufacturer version. Manufacturer identification
number.
PVER
read-only, 6 bit
Protocol version. Specifies version of Direct protocol
supported.
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