參數(shù)資料
型號： HYB25R144180C
廠商： SIEMENS AG
英文描述： 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
中文描述： 144兆位的直接的RDRAM（144兆直接的RDRAM）
文件頁數(shù)： 39/93頁
文件大?。?/td> 919K
代理商： HYB25R144180C
Data Book
39
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Control Register Transactions
The RDRAM has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and
SIO1. These provide serial access to a set of control registers in the RDRAM. These control
registers provide configuration information to the controller during the initialization process. They
also allow an application to select the appropriate operating mode of the RDRAM.
SCK (serial clock) and CMD (command) are driven by the controller to all RDRAMs in parallel. SIO0
and SIO1 are connected (in a daisy chain fashion) from one RDRAM to the next. In normal
operation, the data on SIO0 is repeated on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet). The controller connects to SIO0 of the
first RDRAM.
Figure 23
Serial Write (SWR) Transaction to Control Register
Write and read transactions are each composed of four packets, as shown in
Figure 23
and
Figure 24
. Each packet consists of 16 bits, as summarized in
Figure 15
and
Figure 16
. The packet
bits are sampled on the falling edge of SCK. A transaction begins with a SRQ (Serial Request)
packet. This packet is framed with a 11110000 pattern on the CMD input (note that the CMD bits are
sampled on both the falling edge and the rising edge of SCK). The SRQ packet contains the
SOP3…SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5…SDEV0
(Serial Device address) selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is set, then all
RDRAMs are selected. The SA (Serial Address) packet contains a 12 bit address for selecting a
control register.
A write transaction has a SD (Serial Data) packet next. This contains 16 bits of data that is written
into the selected control register. A SINT (Serial Interval) packet is last, providing some delay for
any side-effects to take place. A read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the control register. The SD read data packet
travels in the opposite direction (towards the controller) from the other packet types. The SCK cycle
time will accommodate the total delay.
SPT04227
T36
SIO1
1111
SIO0
CMD
0000
SCK
T4
Each packet is repeated
from SIO0 to SIO1
SRQ - SWR Command
00000000...00000000
SRQ-SWR Command
SA
00000000...00000000
SA
T20
SD
00000000...00000000
SD
SINT
SINT
00000000...00000000
T52
1
1
0
0
1
1111
0
0
T68
1
Next transaction
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