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參數(shù)資料
| 型號： | HYB25R144180C |
| 廠商： | SIEMENS AG |
| 英文描述： | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| 中文描述： | 144兆位的直接的RDRAM（144兆直接的RDRAM） |
| 文件頁數(shù)： | 33/93頁 |
| 文件大小： | 919K |
| 代理商： | HYB25R144180C |
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Data Book
33
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Write/Retire - Examples
The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first
step consists of transporting the write command, write address, and write data into the write buffer.
The second step happens when the RDRAM automatically retires the write buffer (with an optional
bytemask) into the sense amp. This two-step write process reduces the natural turn-around delay
due to the internal bidirectional data pins.
Figure 17
(left) shows an example of this two step process. The first COLC packet contains the WR
command and an address specifying device, bank and column. The write data dualoct follows a
time
t
CWD
later. This information is loaded into the write buffer of the specified device. The COLC
packet which follows a time
t
RTR
later will retire the write buffer. The retire will happen automatically
unless (1) a COLC packet is not framed (no COLC packet is present and the S bit is zero), or (2) the
COLC packet contains a RD command to the same device. If the retire does not take place at time
t
RTR
after the original WR command, then the device continues to frame COLC packets, looking for
the first that is not a RD directed to itself. A bytemask MSK(a1) may be supplied in a COLM packet
aligned with the COLC that retires the write buffer at time
t
RTR
after the WR command.
The memory controller must be aware of this two-step write/retire process. Controller performance
can be improved, but only if the controller design accounts for several side effects.
Figure 17
Normal Retire (left) and Retire/Read Ordering (right)
Figure 17
(right) shows the first of these side effects. The first COLC packet has a WR command
which loads the address and data into the write buffer. The third COLC causes an automatic retire
of the write buffer to the sense amp. The second and fourth COLC packets (which bracket the retire
packet) contain RD commands with the same device, bank and column address as the original WR
command. In other words, the same dualoct address that is written is read both before and after it
is actually retired. The first RD returns the old dualoct value from the sense amp before it is
overwritten. The second RD returns the new dualoct value that was just written.
Transaction b: RD
Transaction c: RD
Transaction a: WR
DQA8...0
DQB8...0
Transaction a: WR
a1 = {Da, Ba, Ca1}
CWD
t
t
RTR
D (a1)
DQA8...0
DQB8...0
D (a1)
c1 = {Da, Ba, Ca1}
b1 = {Da, Ba, Ca1}
a1 = {Da, Ba, Ca1}
CWD
t
RTR
t
Q (b1)
SPT04221
Q (
WR a1
This RD gets the old data
Retire is automatic here unless:
(1) No COLC packet (S = 0) or
(2) COLC packet is RD to device Da
CTM/CFM
COL0
COL4...
ROW0
ROW2...
WR a1
T2
T0
T1
T3
T4
retire (a1)
MSK (a1)
COL0
COL4...
ROW0
ROW2...
CTM/CFM
T7
T5
T6
T8
T9
T12
T10 T11
T13 T14
T0
T1
This RD gets the new data
CAC
RD b1
MSK (a1)
retire (a1)
t
RD c1
CAC
t
T4
T2
T3
T5
T6
T9
T7
T8
T10 T11
T14
T13
T12
T15 T16
T19
T18
T17
T20 T21
T23
T22
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