參數(shù)資料
型號(hào)： HMS30C2000
英文描述： [Application Specific Solution Product]
中文描述： [專用解決方案產(chǎn)品]
文件頁數(shù)： 97/161頁
文件大?。?/td> 973K
代理商： HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
97
2.7.2.
User Accessible Registers (Base = 0x1800_0000)
This section describes all base, control and status register inside the UART. The address field
indicates a relative address in hexadecimal. The base address of UART0 is 0x18000000 and UART1
is 0x18080000. Only UART1 has a hardware flow control. Width specifies the number of bits in the
register and access specifies the valid access types that register. Where RW stands for read and write
access, RO for read only access. A “C” appended to RW or RO, indicates that some or all of the bits
can be cleared after a write ‘1’ in corresponding bit. Base address for UART 1 is 0x1808_0000.
Table 2.54 Registers for UART
Name
Address Width Access
Description
RHR
0x00
8
RO
Receiver Holding Register
THR
0x00
8
WO
Transmitter Holding Register
IER
0x04
4
RW
Interrupt Enable Register
IIR
0x08
4
RO
Interrupt Identification Register
FCR
0x08
2
WO
FIFO Control Register
LCR
0x0c
7
RW
Line Control Register
MCR
0x10
4
RW
MODEM Control Register
LSR
0x14
8
RO
Line Status Register
MSR
0x18
8
RO
MODEM Status Register
DLL
0x00
8
WO
Divisor Latch LSB Register
DLM
0x04
8
WO
Divisor Latch MSB Register
*DLL and DLM are accessible ONLY when LCR bit-7 is set to “1”
2.7.2.1.
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is
Receiver Holding Register (RHR)
transmitted and received first. Received data is double buffered; this uses an additional shift register
to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the
Receive Buffer register. The shift register is not accessible.
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