
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
39
_008c MAC address 7 (Lower 4 bytes)
_0090 Pause frame address (Higher 2 bytes)
_0094 Pause frame address (Lower 4 bytes)
_0098 Pause frame Type / Op. code
_009c Pause frame delay value
R/W
0000_0000
R/W
0000_0180
R/W
c200_0001
R/W
8808_0001
R/W
0000_0018
_00a0 Transmit buffer base address (High priority)
_00a4 Transmit buffer length (High priority)
_00a8 TX queue buffer level (Low)
R/W
0000_0000
R/W
0000_0000
R
0000_0000
_00ac TX address return (Low)
_00b0 TX queue buffer level (High)
_00b4 TX address return (High)
000b8 – 00ffc RESERVED
1920_1000
R
0000_0000
R
0000_0000
R
0000_0000
0000_0000
. . .
_10c8
Same Configuration as
Enet Mac 0 Controller
Enet
Mac 1
Controller
010cc – ffffc RESERVED
1930_0000 Source Pending Register
0000_0000
R/W
0000_0000
_0004 Interrupt Mode Register
_0008
Interrupt Enable Mask Register
_000c Interrupt Priority Control Register
_0010 Interrupt Pending Register
_0014 Interrupt Offset Register
00018 – ffffc RESERVED
W
0000_0000
R/W
ffff_ffff
W
0000_003f
R/W
0000_0000
R
0000_0020
Interrupt
Controller
Prev_Read_value
1940_0000 Identification Register
_0004 Interface Status Register (VS_in)
_0008 Interface Control Register (VS_out)
_000c General Control Register
_0010 Card Status Change Register
_0014 Card Status Change Enable Register
R
0000_0082
R
0000_0000
R/W
0000_0000
R/W
0000_0001
R
R/W
0000_0000
_0018 Setup Timing 0 Register for Bank 0
_001c Command Timing 0 Register for Bank 0
_0020 Recovery Timing 0 Register for Bank 0
R/W
0000_000f
R/W
0000_000f
R/W
0000_000f
_0024 Setup Timing 1 Register for Bank 1
_0028 Command Timing 1 Register for Bank 1
_002c Recovery Timing 1 Register for Bank 1
R/W
0000_000f
R/W
0000_000f
PCMCIA
Controller
R/W
0000_000f