參數(shù)資料
型號: HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [專用解決方案產(chǎn)品]
文件頁數(shù): 108/161頁
文件大?。?/td> 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
108
2.8.
TIMER
The HMS30C7110 integrates 3 channels of Timers and each channel has 32-bit down counter. The
input clock of each channel is selectable among one of the 4 clock speeds, System Bus Clock/1,
System Bus Clock/4, System Bus Clock/16, or System Bus Clock/256. When the clock of the
system bus is 100MHz, the Timer input options are 100/25/6.25/0.4MHz. When the clock of the
system is 80MHz, the Timer input options are 80/20/5/0.3125MHz. The Timers are fully
configurable through a set of control registers. Complete descriptions of these registers are given in
the Register Section.
2.8.1.
User Accessible Registers (Base = 0x1810_0000)
This section describes all base, control and status registers inside the Timer. The address field
indicates a relative address in hexadecimal. Width specifies the number of bits in the register and
access specifies the valid access types that register. Where ‘RW’ stands for read and write access,
‘RO’ for read only access. A ‘C’ appended to ‘RW’ or ‘RO’, indicates that some or all of the bits can
be cleared after a write ‘1’ in corresponding bit.
Table 2.68 Registers for TIMER
Name
Address Width
Access
Description
Clock Selection
0x00
3x2
RW
Input clock selection for 3 channels
Timer Control
0x04
3x2
RW
Channel enable/disable
Timer Interval 0
0x08
32
RW
Reload value for Timer Channel 0
Timer Interval 1
0x0c
32
RW
Reload value for Timer Channel 1
Timer Interval 2
0x10
32
RW
Reload value for Timer Channel 2
Timer Value 0
0x14
32
RW
Channel 0 current timer value
Timer Value 1
0x18
32
RW
Channel 1 current timer value
Timer Value 2
0x1c
32
RW
Channel 2 current timer value
INT SRC
0x20
3
RW
Interrupt pending register
INT ENABLE
0x24
3
RW
Interrupt enable register
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