參數(shù)資料
型號: HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [專用解決方案產(chǎn)品]
文件頁數(shù): 116/161頁
文件大?。?/td> 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
116
Table 2.80 The Bit Definition of the Interrupt Enable Register
Address :
1820_0010
Bits
Access
Default Description
31: 16
0x00
Reserved
15: 0
RW
0x00
INT ENABLE
This 16-bits field enables the GPI interrupts.
0 = disable
1 = enable
2.9.1.6.
INT MODE
The interrupt mode register chooses the interrupt mode of either level trigger or edge trigger.
Table 2.81 Interrupt Mode Register Bit Definition
Address :
1820_0014
Bits
Access
Default Description
31: 16
0x00
Reserved
15: 0
RW
0x00
INT MODE
This 16-bits field controls the interrupt mode of each GPI pins.
0 = Level trigger
1 = Edge trigger
2.9.1.7.
INT LEVEL
The interrupt level register selects active level of interrupt sources when in level triggering mode,
active low or active high.
Table 2.82 Interrupt Level Register Bit Definition
Address :
1820_0018
Bits
Access Default Description
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