
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
71
that some or all of the bits are auto cleared. Base address of Ethernet MAC 1 is 0x1920_1000.
Table 2.22 Registers for Ethernet MAC
Name
Address Width
Access
Description
MAC_MODE
0x00
32
RW
MAC mode register
INT_SRC
0x04
32
RW
Interrupt source register
INT_ENABLE
0x08
32
RW
Interrupt enable register
IF_GAP
0x0C
32
RW
Inter-frame gap register
COLL_CFG
0x10
32
RW
Collision control register
TX_BADDR
0x14
32
RW
Transmit buffer base address
TX_LENGTH
0x18
32
RW
Transmit buffer length
RX_BADDR
0x1C
32
RW
Receive buffer base address
RX_BSTAT
0x20
32
RO
Receive buffer status
RX_BUFLVL
0x24
32
RO
Address/Status buffer level
RX_ADDR_BACK 0x28
32
RO
Receive buffer base address return
CTRL_MODE
0x2C
32
RWC
Control mode register
MII_MODE
0x30
32
RW
MII mode register
MII_CMD
0x34
32
RWC
MII command register
MII_TXDATA
0x38
32
RW
MII transmit data
MII_RXDATA
0x3C
32
RW
MII receive data
RESERVED
0x40
32
Reserved
LENGTH
0x44
32
RW
Max, Min, burst length register
MCAST_ADDR_0 0x48
32
RW
Multicast Address (Most significant)
MCAST_ADDR_1 0x4C
32
RW
Multicast Address (Least significant)
MAC_ADDR_00
0x50
32
RW
MAC address 0 (Most significant 2 bytes)
MAC_ADDR_01
0x54
32
RW
MAC address 0 (Least significant 4 bytes)
MAC_ADDR_10
0x58
32
RW
MAC address 1 (Most significant 2 bytes)
MAC_ADDR_11
0x5C
32
RW
MAC address 1 (Least significant 4 bytes)
MAC_ADDR_20
0x60
32
RW
MAC address 2 (Most significant 2 bytes)
MAC_ADDR_21
0x64
32
RW
MAC address 2 (Least significant 4 bytes)
MAC_ADDR_30
0x68
32
RW
MAC address 3 (Most significant 2 bytes)