參數(shù)資料
型號(hào): HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [專用解決方案產(chǎn)品]
文件頁數(shù): 148/161頁
文件大小: 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
148
0
RO
0x1
IO access enable
This 1 bit field is fixed to logic 1 because the bridge always supports
the I/O area accessing.
2.13.1.16.
Status for CardBus
This register will be cleared when it is read.
Table 2.121 Status Bit Definition
Address :
1948_0004
Bits
Access Default Description
31:16
0x0
Reserved
15
RO
0x0
Detected parity error
This 1 bit field is set when nCPERR pin is asserted.
14
RO
0x0
Received system error
This 1 bit field is set when nCSERR pin is asserted.
13
RO
0x0
Received master abort
This 1 bit field is set when the bridge get the master abort signaling
from the PC card.
12
RO
0x0
Received target abort
This 1 bit field is set when the bridge get the target abort signaling
from the PC card.
11
RO
0x0
Signaled target abort
This 1 bit field is set when the bridge make a target abort signaling.
10
RO
0x1
DEVSEL timing
This 1 bit field is fixed to 0x1 and that means the bridge operates as
a medium slave.
9
RO
0x0
Data parity detected
This bit will be set when Bridge detected parity error condition in
data phase
8
RO
0x0
Fast back to back capable
The CardBus bridge doesn’t support fast back to back transactions.
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