參數(shù)資料
型號: HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [專用解決方案產(chǎn)品]
文件頁數(shù): 102/161頁
文件大?。?/td> 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
102
Table 2.61 LCR Bit Definition
Address :
1800_000C
Bits
Access Default Description
31:8
0x00
Reserved
7
RW
0x0
Divisor latch enable
0 = disable
1 = enable
6
RW
0x0
BREAK CONTROL
It causes a break condition to be transmitted to the receiving UART.
When it is set to logic 1, the serial output is forced to the Spacing
state (logic 0). The break is disabled by setting this bit to logic 0.
5
RW
0x0
PARITY ENABLE
When this bit is logic 1, a Parity bit is generated (transmit data) or
checked (receive data) between the last data bit and Stop bit of the
serial data.
4:3
RW
0x00
PARITY SELECT
0 = odd parity
1 = even parity
2 = forced one (Mark parity)
3 = forced zero (Space parity)
2
RW
0x0
STOP BIT LENGTH
This bit specifies the number of Stop bits transmitted or received
serial character.
0 = 1 stop bit
1 = 2 stop bit
1: 0
RW
0x00
WORD LENGTH
These two bits specify the number of data bits in each transmitted or
received serial character. The encoding of bits 0 and 1 is as follows:
0 = 5 bits / character
1 = 6 bits / character
2 = 7 bits / character
3 = 8 bits / character
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