參數(shù)資料
型號: HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [專用解決方案產(chǎn)品]
文件頁數(shù): 103/161頁
文件大小: 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
103
2.7.2.7.
This register controls the interface with the MODEM or data set. Details on each bit follow:
MODEM Control Register (MCR)
Table 2.62 MCR Bit Definition
Address :
1800_0010
Bits
Access Default Description
31:6
0x00
Reserved
5
RW
0x0
AUTOFLOW
When this bit is set, the auto-flow control is enabled. The auto-flow
control can be configured by setting bit 1 and 5 of MCR as shown in
Table 2.68.
4
RW
0x0
LOOPBACK Enable
This bit provides a local loop-back feature for diagnostic testing of
the associated serial channel.
3:2
0x00
Reserved
1
RW
0x0
RTS Control
This bit controls the Request to Send (RTS#) output. Bit 1 affects the
RTS# output in a manner identical to that described below for bit 0.
0
RW
0x0
DTR Control
This bit controls the Data Terminal Ready (DTR#) output. When bit
0 is set to logic 1, the DTR# output is forced to a logic 0. When bit 0
is reset to logic 0, the DTR# output is forced to logic 1.
Table 2.63 Autoflow Control Configuration
Bit5
Bit1
Description
1
1
Auto-rts and auto-cts enabled
1
0
Auto-cts only enabled
0
X
Auto-rts and auto-cts disabled
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