參數(shù)資料
型號： HMS30C2000
英文描述： [Application Specific Solution Product]
中文描述： [專用解決方案產(chǎn)品]
文件頁數(shù)： 101/161頁
文件大?。?/td> 973K
代理商： HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
101
2.7.2.5.
This is a write only register at the same location as the IIR (the IIR is a read only register). This
FIFO Control Register (FCR)
register is used to enable the FIFOs, clear the FIFOs, set the RCVR FIFO trigger level, and select
the type of DMA signaling.
Table 2.60 FCR Bit Definition
Address :
1800_0008
Bits
Access Default Description
31:8
0x00
Reserved
7:6
WO
0x00
These two bits are used to designate the interrupt trigger level. When
the number of bytes in the RCVR FIFO is equivalent to the
designated interrupt trigger level, a Received Data Available
Interrupt is activated. This interrupt must be enabled by setting IER0
0 = RCVR FIFO Trigger Level is 1
1 = RCVR FIFO Trigger Level is 4
2 = RCVR FIFO Trigger Level is 8
3 = RCVR FIFO Trigger Level is 14
5:3
0x00
Reserved
2
WO
0x0
Writing a 1 to FCR2 clears all bytes in the XMIT FIFO and resets its
counter logic to 0. The shift register is not cleared. The 1 that is
written to this bit position is self-clearing
1
WO
0x0
Writing a 1 to FCR1 clears all bytes in the RCVR FIFO and resets its
counter logic to 0. The shift register is not cleared. The 1 that is
written to this bit position is self-clearing.
0
0x0
Reserved
2.7.2.6.
The system programmer specifies the format of the asynchronous data communications exchange
Line Control Register (LCR)
and sets the Divisor Latch Access bit via the Line Control Register (LCR). This is a read and write
register. Details on each bit follow:
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