參數(shù)資料
型號: HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [專用解決方案產(chǎn)品]
文件頁數(shù): 54/161頁
文件大?。?/td> 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
54
Table 2.13 Registers for ROM controller
Name
Address Width
Access
Description
Configuration 0
0x00
32
RW
Timing configuration of bank 0
Configuration 1
0x04
32
RW
Timing configuration of bank 1
Configuration 2
0x08
32
RW
Timing configuration of bank 2
2.4.2.1.
Configuration 0~3
These registers include timing information for all banks.
Table 2.14 Configuration Registers Bit Definition
Address :
1900_0000, 1900_0004, 1900_0008
Bits
Access Default Description
31:30
0
Reserved
29:28 RW
0
BUS MODE
00 = A/D non-mux style
01 = A/D mux Intel style
10 = A/D mux, Motorola style
11 = Reserved
27
RW
0
WAIT ENABLE
This 1 bit field accepts/denies the external wait (GPIO2/Wait) signal pin
expending the access time.
0 = disable
1 = enable
26
RW
0
This bit selects the active level of wait signal, which would be connected
to GPIO2/Wait on pin 206. Each setting for each Configuration register
affect only on assigned address range.
0 = active low input
1 = active high input
25:24 RW
0x3
DATA BUS WIDTH
00 = 8 bit wide bus
01 = 16 bit wide bus
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