參數(shù)資料
型號: HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [專用解決方案產(chǎn)品]
文件頁數(shù): 49/161頁
文件大?。?/td> 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
49
Bits
Access Default Description
31: 0
RW
0x0
Interval (Write) or Current WDT counter value (Read)
This 32-bit field contains the interval value that will be loaded to down
counter periodically.
2.3.2.4.
Main PLL Control
The main PLL control register selects the operating mode of PLL. Refer to H25PL12S Data sheet
for more detailed information about PLL control.
Table 2.11 Main PLL Control
Address :
1830_000C
Bits
Access Default Description
31:29 RW
0x5
lfm : loop filter mode selector.
** Use default value for normal operation, set 0x7 only if external filter
logic is used for lower frequency (< 150KHz).
28:15 RW
0x0c
m : Feedback divisor
14:7
RW
0x1
n : Reference divisor
VCO clock frequency will be determined with M and N based on
following equation: F
vco
= F
ref
x (m+2) / (n+1)
As a default, F
vco
= 10MHz x (12+2) / (1+1) = 70MHz.
6:5
RW
0x0
p : Post divisor
This field defines division factor after VCO. For example, if p=1 and
vco output frequency is 20MHz, final PLL output frequency will be
10MHz (F
pll
= F
vco
/ (p+1) )
4
RW
0x0
pd : PLL power down mode except VCO
If set to “1”, PLL will not generate clock though VCO is still working.
3:2
RW
0x1
vc : VCO range control vector
This field defines operation range of VCO.
00 : 40MHz – 100MHz
01 : 60MHz – 120MHz
10 : 80MHz – 140MHz
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