8 GHz fractionaL-n PLL For price, deli" />
參數(shù)資料
型號(hào)： HMC704LP4E
廠商： Hittite Microwave Corporation
文件頁(yè)數(shù)： 9/44頁(yè)
文件大?。?/td> 0K
描述： IC FRACT-N PLL 16BIT 24QFN
標(biāo)準(zhǔn)包裝： 1
類型： 整數(shù) N/小數(shù) N 分頻
PLL： 是
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/無
頻率 - 最大： 8GHz
除法器/乘法器： 是/無
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 1127-1066-6
P
LL
s
-
s
M
T
5 - 17
HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
nfpd
(n+1)fpd
Integer
Boundary
fVCO
Δ
Integer
Boundary
n = integer
d = 0
m = 1 = 1st order
Δ < Loop Bandwidth
1st Order Integer Boundary spur
(n+1)fpd
fVCO
Δ
Integer
Boundary
n = integer
d = 1
m = 2 = 2nd order
Δ < Loop Bandwidth
2nd Order spur
2Δ
Integer
Boundary
Figure 26. Fractional Spurious Example
(n+1/2)fpd
nfpd
Characterization of the levels and orders of these products is not unlike a mixer spur chart. Exact levels of the products
are dependent upon isolation of the various PLL parts. Hittite can offer guidance about expected levels of spurious with
our PLL and VCO application boards. Regulators with high power supply rejection ratios (PsRR) are recommended,
especially in noisy applications.
When operating in fractional mode, charge pump and phase detector linearity is of paramount importance. Any non-
linearity degrades phase noise and spurious performance. Phase detector linearity degrades when the phase error is
very small and is operating back and forth between reference lead and VCO lead. To mitigate these non-linearities in
fractional mode it is critical to operate the phase detector with some finite phase offset such that either the reference or
VCO always leads. To provide a finite phase error, extra current sources can be enabled which provide a constant DC
current path to VDD (VCO leads always) or ground (reference leads always). These current sources are called charge
pump offset and they are controlled via “Reg 09h”. The time offset at the phase detector should be ~2.5ns + 4Tps, where
Tps is the RF period at the fractional prescaler input in nanoseconds (ie. after the optional fixed divide by 2). The spe-
cific level of charge pump offset current is determined by this time offset, the comparison frequency and the charge
pump current and can be calculated from:
Operation with charge pump offset influences the required configuration of the Lock Detect function. Refer to the de-
scription of “PD Window Based Lock Detect” later in this document. Note that this calculation can be performed for the
center frequency of the VCO, and does not need refinement for small differences (<25%) in center frequencies.
Another factor in the spectral performance in Fractional Mode is the choice of the Delta-sigma Modulator mode. Mode
A can offer better in-band spectral performance (inside the loop bandwidth) while Mode B offers better out of band per-
formance. see “Reg 06h”[3:2] for DsM mode selection. Finally, all fractional PLLs create fractional spurs at some level.
Hittite offers the lowest level fractional spurious in the industry in an integrated solution.
(
)
(
)
9
Required CP Offset ( A) = 2.5 10
4
(sec)
(
)
(
)
PS
comparison
CP
T
F
Hz
I
A
×
+
×
(EQ 4)
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