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參數(shù)資料
| 型號(hào)： | HMC704LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 17/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1127-1066-6 |
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5 - 24
HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
Given a DC phase offset as described in the above example, when in lock, the divided VCO will arrive at the PD about
4nsec after the divided Reference. The Lock Detect Window always starts on the arrival of the first signal at the PD, in
this case the Reference. The Lock Detect window must be longer than 4ns+4Tps and shorter than the period of the PD,
in this example, 20nsec.
A comfortable solution of 8.9ns with timer speed set at “Reg 07h”[11:10]=1 and Timer divider “Reg 07h”[9:7]=1 works
well for the example PD frequency and charge pump offset setting.
Tolerance on the window is +25% at +85C, -25% at -40C. Here 8.9ns nominal window may extend by +25% at +85C to
11.1ns, which is fine for a PD period of 20ns. Also the minimum window may shrink by 25% to 6.7ns at -40C, which
again works well for the DC offset of 4.0ns (worst case instantaneous phase offset of 5.5ns).
There is always a good solution for the lock detect window for a given operating point. The user should understand
however that one solution does not fit all operating points. If charge pump offset or PD frequency are changed signifi-
cantly then the lock detect window may need to be adjusted.
cycle Slip Prevention (cSP)
When changing frequency and the VCO is not yet locked to the reference, the instantaneous frequencies of the two PD
inputs are different, and the phase difference of the two inputs at the PD varies rapidly over a range much greater than
+/-2π radians. since the gain of the PD varies linearly with phase up to +/-2π, the gain of a conventional PD will cycle
from high gain, when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is
slightly larger than 0 radians. The output current from the charge pump will cycle from maximum to minimum even
though the VCO has not yet reached its final frequency.
The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle. This can
make the VCO frequency actually reverse temporarily during locking. This phenomenon is known as cycle slipping.
Cycle slipping causes the pull-in rate during the locking phase to vary cyclically. Cycle slipping increases the time to
lock to a value much greater than that predicted by normal small signal Laplace analysis.
The PLL PD features an ability to reduce cycle slipping during acquisition. The Cycle slip Prevention (CsP) feature in-
creases the PD gain during large phase errors. The specific phase error that triggers the momentary increase in PD
gain is set via “Reg 0Bh”[8:7].
Ref at PD
VCO at PD
LD WINDOW
PD Period 20ns
VCO Offset 4ns
LD Window 8.9ns+/-25%
+Window Margin
-Window Margin
Figure 33. Lock Detect Window Example with 50MHz PD and 4ns VCO Offset
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| HMC704LP4ETR | 制造商:Hittite Microwave Corp 功能描述:IC FRACT-N PLL 16BIT 24QFN |
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| HMC705LP4ETR | 功能描述:IC DIVIDER HBT PROGR 24QFN 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 功能:分頻器 頻率:100MHz ~ 6.5GHz RF 類型:- 輔助屬性:- 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-QFN（4x4） 標(biāo)準(zhǔn)包裝:1 |
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