8 GHz fractionaL-n PLL For price, deli" />
參數(shù)資料
型號(hào)： HMC704LP4E
廠商： Hittite Microwave Corporation
文件頁(yè)數(shù)： 6/44頁(yè)
文件大?。?/td> 0K
描述： IC FRACT-N PLL 16BIT 24QFN
標(biāo)準(zhǔn)包裝： 1
類型： 整數(shù) N/小數(shù) N 分頻
PLL： 是
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 8GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 1127-1066-6
p
ll
s
-
s
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T
5 - 14
HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
where:
p
2
Phase Noise Contribution of the PLL (rads2/Hz)
fo
Frequency of the VCO (Hz)
fpd
Frequency of the Phase Detector (Hz)
fm
Frequency offset from the carrier (Hz)
Fpo
Figure of Merit (FOM) for the phase noise floor
Fp1
Figure of Merit (FOM) for the flicker noise region
PLL Noise Floor
PLL 1/f Flicker Noise
VCO 1/f2 Noise
VCO 1/f3 Noise
Typical Closed Loop Phase Noise
LOG OFFSET FREQUENCY (fm)
PHA
SE
NOISE
(dBc/Hz)
Closed Loop
Bandwidth
Figure 24. Figures of Merit Noise Models for the PLL
If the free running phase noise of the VCO is known, it may also be represented by a figure of merit for both 1/f2 , Fv2,
and the 1/f3, Fv3, regions.
The Figures of Merit are essentially normalized noise parameters for both the PLL and VCO that can allow quick esti-
mates of the performance levels of the PLL at the required VCO, offset and phase detector frequency. Normally, the
PLL IC noise dominates inside the closed loop bandwidth of the PLL, and the VCO dominates outside the loop band-
width at offsets far from the carrier. Hence a quick estimate of the closed loop performance of the PLL can be made by
setting the loop bandwidth equal to the frequency where the PLL and free running phase noise are equal.
The Figure of Merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such as
Hittite PLL Design, which can give a much more accurate estimate of the closed loop phase noise and PLL loop filter
component values.
Given an optimum loop design, the approximate closed loop performance is simply given by the minimum of the PLL
and VCO noise contributions.
Φ
(
)
0
1
2
0
2
0 ,,
d
p
m
pd
mf
Ff
f f f
ff
Φ=
+
PLL Phase Noise
Contribution
(EQ 1)
(EQ 2)
(
)
3
2
0
2
0
23
,
m
mm
Ff
f f
ff
ν
Φ=
+
VCO Phase Noise
Contribution
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