8 GHz fractionaL-n PLL For price, deli" />
參數(shù)資料
型號(hào): HMC704LP4E
廠商: Hittite Microwave Corporation
文件頁(yè)數(shù): 37/44頁(yè)
文件大?。?/td> 0K
描述: IC FRACT-N PLL 16BIT 24QFN
標(biāo)準(zhǔn)包裝: 1
類型: 整數(shù) N/小數(shù) N 分頻
PLL:
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 8GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.3V,5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 1127-1066-6
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5 - 42
HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
table 23. reg 0ah auxSPi trigger register
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[11:0]
R/W
Reserved
12
0
Reserved
[12]
R/W
No AuxsPI Trigger
1
0
No AuxsPI trigger on Reg5 Write
[15:13]
R/W
reserved
3
0
Reserved
[16]
R/W
Force RDivider Bypass
1
0
Force the R Divider Bypass, ignore Reg03
table 24. reg 0Bh PD register
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[2:0]
R/W
pd_del_sel
3
1
sets PD reset path delay
[3]
R/W
short PD Inputs
1
0
shorts the inputs to the Phase Detector - Test Only
[4]
R/W
pd_Invert
1
0
Inverts the PD polarity
0 - Use with a positive tuning slope VCO and passive loop filter
(default).
1 - Use with a negative slope VCO or with an inverting active loop
filter with a positive slope VCO.
[5]
R/W
pd_up_en
1
Enables the PD UP output, see also Reg0B[9]
[6]
R/W
pd_dn_en
1
enables the PD DN output, see also Reg0B[9]
[8:7]
R/W
CsP Mode
2
0
Cycle slip Prevention Mode
0: CsP Disabled
1: CP Gain increased if Phase Error > 2 nsec
2: CP Gain increased if Phase Error > 4 nsec
3: CP Gain increased if Phase Error > 6 nsec
[9]
R/W
Force CP UP
1
0
Forces CP UP output on - Use for Test only
[10]
R/W
Force CP DN
1
0
Forces CP DN output on - Use for Test only
[11]
R/W
Force CP MId Rail
1
0
Force CP MId Rail - Use for Test only
[14:12]
R/W
Ps Bias
3
0
Prescaler Bias
0: Nominal
1: +20% RF Buffer
2: +25% Rsync
3: +50%
[16:15]
R/W
CP Internal OpAmp Bias
2
3
CP Internal OpAmp Bias
[18:17]
R/W
MCounter Clock Gating
2
3
MCounter Clock Gating
0: MCounter Off for N<32
1: N<128
2: N< 1023
3: All Clocks ON
[19]
R/W
Reserved
1
[21:20]
R/W
Divider Pulse Width
2
0
0: shortest, ... 3: Longest
[23:22]
R/W
Reserved
2
0
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