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參數(shù)資料
| 型號(hào)： | HMC704LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 8/44頁 |
| 文件大小： | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1127-1066-6 |
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HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
It should be noted that actual phase noise near the corner frequency of the loop bandwidth is affected by loop parame-
ters and one should use a more complete design tool such as Hittite PLL Design for better estimates of the phase noise
performance. Noise models for each of the components in Hittite PLL Design can be derived from the FOM equations
or can be provided by Hittite applications engineering.
Spurious Performance
integer operation
The VCO always operates at an integer multiple of the PD frequency in an integer PLL. In general spurious signals
originating from an integer PLL can only occur at multiples of the PD frequency. These unwanted outputs are often sim-
ply referred to as reference sidebands.
spurs unrelated to the reference frequency must originate from outside sources. External spurious sources can modu-
late the VCO indirectly through power supplies, ground, or output ports, or bypass the loop filter due to poor isolation of
the filter. It can also simply add to the output of the PLL.
The HMC704LP4E has been designed and tested for ultra-low spurious performance. Reference spurious levels are
typically below -100dBc with a well designed board layout. A regulator with low noise and high power supply rejection,
such as the HMC860LP3E, is recommended to minimize external spurious sources.
Reference spurious levels of below -100dBc require superb board isolation of power supplies, isolation of the VCO from
the digital switching of the PLL and isolation of the VCO load from the PLL. Typical board layout, regulator design, demo
boards and application information are available for very low spurious operation. Operation with lower levels of isola-
tion in the application circuit board, from those recommended by Hittite, can result in higher spurious levels.
Of course, if the application environment contains other interfering frequencies unrelated to the PD frequency, and if
the application isolation from the board layout and regulation are insufficient, then the unwanted interfering frequencies
will mix with the desired PLL output and cause additional spurs. The level of these spurs is dependant upon isolation
and supply regulation or rejection (PsRR).
fractional operation
Unlike an integer PLL, spurious signals in a fractional PLL can occur due to the fact that the VCO operates at frequen-
cies unrelated to the PD frequency. Hence intermodulation of the VCO and the PD harmonics can cause spurious side-
bands. spurious emissions are largest when the VCO operates very close to an integer multiple of the PD. When the
VCO operates exactly at a harmonic of the PD then, no in-close mixing products are present.
Interference is always present at multiples of the PD frequency, fpd, and the VCO frequency, fvco. If the fractional mode
of operation is used, the difference, Δ, between the VCO frequency and the nearest harmonic of the reference, will cre-
ate what are referred to as integer boundary spurs. Depending upon the mode of operation of the PLL, higher order,
lower power spurs may also occur at multiples of integer fractions (sub-harmonics) of the PD frequency. That is, frac-
tional VCO frequencies which are near nfpd + fpdd/m, where n, d and m are all integers and d<m (mathematicians refer
to d/m as a rational number). We will refer to fpdd/m as an integer fraction. The denominator, m, is the order of the spuri-
ous product. Higher values of m produce smaller amplitude spurious at offsets of mΔ and usually when m>4 spurs are
very small or unmeasurable.
The worst case, in fractional mode, is when d=0, and the VCO frequency is offset from nfpd by less than the loop band-
width. This is the “in-band fractional boundary” case.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMC704LP4ETR | 制造商:Hittite Microwave Corp 功能描述:IC FRACT-N PLL 16BIT 24QFN |
| HMC705LP4 | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:6.5 GHz PROGRAMMABLE DIVIDER (N = 1 - 17) |
| HMC705LP4E | 制造商:Hittite Microwave Corp 功能描述:IC DIVIDER HBT PROGR 24-QFN |
| HMC705LP4ETR | 功能描述:IC DIVIDER HBT PROGR 24QFN 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 功能:分頻器 頻率:100MHz ~ 6.5GHz RF 類型:- 輔助屬性:- 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-QFN（4x4） 標(biāo)準(zhǔn)包裝:1 |
| hmc706lc3c | 制造商:Hittite Microwave Corp 功能描述:IC CONV NRZ-RZ 13GBPS 16SMD |
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