8 GHz fractionaL-n PLL For price, deli" />
參數(shù)資料
型號： HMC704LP4E
廠商： Hittite Microwave Corporation
文件頁數(shù)： 16/44頁
文件大?。?/td> 0K
描述： IC FRACT-N PLL 16BIT 24QFN
標準包裝： 1
類型： 整數(shù) N/小數(shù) N 分頻
PLL： 是
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/無
頻率 - 最大： 8GHz
除法器/乘法器： 是/無
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VQFN 裸露焊盤
供應商設備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 標準包裝
其它名稱： 1127-1066-6
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HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
Lock Detect operation with Phase offset
When operating in fractional mode the linearity of the charge pump and phase detector are much more critical than in
integer mode. The phase detector linearity degrades when operated with zero phase offset. Hence in fractional mode it
is necessary to offset the phase of the reference and VCO at the phase detector. In such a case, for example with an
offset delay, as shown in Figure 32, the VCO arrival may always occur after the reference. The lock detect circuit win-
dow may need to be adjusted to allow for the delay being used, if the delay is large.
VCO AT PD with FRAC Jitter
LOCK
DETECT
WINDOW
Twindow ~ +10nsec
Figure 32. Lock Detect Window - Fractional Mode with Offset
REF PHAsE ARRIVAL
FRACTIONAL MODE
VCO ARRIVAL DIsTRIBUTION AT PD
PHAsE JITTER
LOCK WINDOW
AVG VCO PHAsE OFFsET
AVG PHAsE OFFsET
FRACTIONAL MODE
AVG VCO PHAsE OFFsET
REF PHAsE ARRIVAL
AVG PHAsE OFFsET
AT PD
In integer mode, 0 offset is recommended. In fractional mode, the time offset should be set to ~ 2.5ns + 4Tps, where Tps
is the RF period at the fractional prescaler input (i.e. after the optional fixed divide by 2). Refer to the Fractional Opera-
tion section for further details about calculating charge pump offset currents
Digital Lock Detect with Digital Window Example
Typical Digital Lock detect window widths are shown in Table 7. Lock Detect windows typically vary +/-10% vs voltage
and +/-15% over -40C to +85C.
table 7. typical Digital Lock Detect Window
LD Timer speed
Reg07[11:10]
Digital Lock Detect Window
Nominal Value +/-25%
(nsec)
Fastest 00
6.5
8.0
11.0
17
29
53
100
195
01
7.0
8.9
12.8
21
36
68
130
255
10
7.1
9.2
13.3
22
38
72
138
272
slowest 11
7.6
10.2
15.4
26
47
88
172
338
LD Timer Divider setting
Reg07[9:7]
0
1
2
3
4
5
6
7
LD Timer Divider Value
0.5
1
2
4
8
16
32
64
As an example if we operate in fractional mode, with a 50MHz PD, a 2700 MHz VCO and a Charge pump gain of 2mA
(“Reg 09h”), based on the previous example, we should set the DC phase offset near 2.5ns+4x370ps =4ns, or 20% of
the 20ns reference period. It becomes a larger proportion with increasing fpd. The offset current is therefore 20% x
2mA=400uA. The polarity of the offset should be chosen so that the VCO lags the reference for the most consistent
results. For non-inverting /inverting loop filter configurations, we recommend down/up offsets, respectively.
REFERENCE
sIGNAL
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