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參數(shù)資料
| 型號： | HMC704LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 15/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標準包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | 1127-1066-6 |
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HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
analog Window Lock Detect
The lock detect window may be generated by either an analog circuit or a digital one-shot circuit. Clearing “Reg
07h”[6]=0 will result in a fixed, analog, nominal 10nsec window, as shown in Figure 31. The analog window cannot be
used if the PD rate is very high, for example near 100MHz, or if the charge pump offset current results in an offset larger
than 7nsec.
For example a 25MHz PD rate with a 1mA charge pump setting (“Reg 09h”[6:0]=”Reg 09h”[13:7]= 50d) and a -400uA
offset current “Reg 09h”[20:14]=80d), would have a phase offset of about 400/1000 = 40% of the PD period or about
16nsec. In such an extreme case the divided VCO would arrive 16ns after the PD reference, and would always arrive
outside of the 10nsec lock detect window. In such a case the lock detect circuit would always read unlocked, even
though the VCO might be locked. The charge pump current, reference period, charge pump offset current, and lock
detect window are related.
Digital Window Lock Detect
setting “Reg 07h”[6]=1 will result in a variable length lock detect window based upon the internal digital timer. The one
shot timer period is controlled by “Reg 07h”[11:10]. The resulting lock detect window period is then generated by the
number of timer periods defined in “Reg 07h”[9:7].
Declaration of Lock
“Reg 07h”[2:0] defines the number of consecutive counts of the divided VCO that must land inside the lock detect win-
dow to declare lock. If for example we set “Reg 07h”[2:0] =5 then the VCO arrival would have to occur inside the widow
2048 times in a row to be declared locked, which would result in a Lock Detect Flag high. A single occurrence outside of
the window will result in an out of lock, i.e. Lock Detect Flag low. Once low, the Lock Detect Flag will stay low until the
lkd_wincnt_max = 2048 condition is met again.
The Lock Detect Flag status is always readable in “Reg 12h”[1]. Lock Detect status is also output to the LD_sDO pin if
“Reg 0Fh”[4:0]=1, “Reg 0Fh”[6]=1 and “Reg 0Fh”[7]=1. Clearing”Reg 0Fh”[6]=0 will display the Lock Detect Flag on
LD_sDO except when a serial port read is requested, in which case the pin reverts temporarily to the serial Data Out
pin and returns to the Lock Detect Flag after the read is completed. Timing of the Lock Detect function is shown in Fig-
ure 31 and Figure 32.
50MHz PD
VCO with Jitter
LOCK
DETECT
WINDOW
Twindow = 10nsec
Figure 31. Normal Lock Detect Window - Integer Mode, Zero Offset
AVG PHAsE OFFsET ~ 0
INTEGER MODE
PHAsE JITTER
LOCK WINDOW
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