8 GHz fractionaL-n PLL For price, deli" />
參數(shù)資料
型號: HMC704LP4E
廠商: Hittite Microwave Corporation
文件頁數(shù): 27/44頁
文件大?。?/td> 0K
描述: IC FRACT-N PLL 16BIT 24QFN
標準包裝: 1
類型: 整數(shù) N/小數(shù) N 分頻
PLL:
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 8GHz
除法器/乘法器: 是/無
電源電壓: 3.3V,5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VQFN 裸露焊盤
供應商設備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 標準包裝
其它名稱: 1127-1066-6
P
LL
s
-
s
M
T
5 - 33
HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
open Mode - Serial Port WritE operation
AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V
table 11. SPi open Mode - Write timing characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
t2
t3
t4
t5
sDI setup time
sDI hold time
sEN low duration
sEN high duration
sCLK 32 Rising Edge to sEN Rising Edge
serial port Clock speed
3
1
10
DC
50
ns
MHz
A typical WRITE cycle is shown in Figure 38.
a. The Master (host) places 24 bit data, d23:d0, MsB first, on sDI on the first 24 falling edges of sCLK.
b. the slave (PLL) shifts in data on sDI on the first 24 rising edges of sCLK
c. Master places 5 bit register address to be written to, r4:r0, MsB first, on the next 5 falling edges of
sCLK (25-29)
d. slave shifts the register bits on the next 5 rising edges of sCLK (25-29).
e. Master places 3 bit chip address, a2:a0, MsB first, on the next 3 falling edges of sCLK (30-32).
Hittite reserves chip address a2:a0 = 000 for all RF PLL-VCOs.
f.
slave shifts the chip address bits on the next 3 rising edges of sCLK (30-32).
g. Master asserts sEN after the 32nd rising edge of sCLK.
h. slave registers the sDI data on the rising edge of sEN.
i.
Master clears sEN to complete the WRITE cycle.
t1
Figure 38. Open Mode - Serial Port Timing Diagram - WRITE
sCLK
sDI
d22
d2
d1
d0
r4
r3
a2
a1
a0
x
r0
2
3
22
23
24
25
26
31
32
x
t2
sEN
t4
t5
t3
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