8 GHz fractionaL-n PLL For price, deli" />
參數(shù)資料
型號(hào): HMC704LP4E
廠商: Hittite Microwave Corporation
文件頁數(shù): 20/44頁
文件大?。?/td> 0K
描述: IC FRACT-N PLL 16BIT 24QFN
標(biāo)準(zhǔn)包裝: 1
類型: 整數(shù) N/小數(shù) N 分頻
PLL:
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 8GHz
除法器/乘法器: 是/無
電源電壓: 3.3V,5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 1127-1066-6
P
LL
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s
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5 - 27
HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
In this example the output frequency of 2,300,000,002.98Hz is achieved by programming the 16 bit binary value of 46d
= 002Eh = 0000 0000 0010 1110 into dsm_intg.
similarly the 24 bit binary value of the fractional word is written into dsm_frac,
1d = 000 001h = 0000 0000 0000 0000 0000 0001
Example 2: set the output to 7.650 025 GHz using a 100MHz reference, R=2.
Here, output is greater than 4GHz, so we enable the internal divide by 2, d = 1. Find the nearest integer value Nint. Nint =
76, 2fint = 7.600 000GHz
This leaves the fractional part to be 2ffrac =50.025MHz
24
6
2
2 50.025 10
8392802.3
2
2 100 10
frac
d
xtal
Rf
N
f
×
=
×
since Nfrac must be an integer number, we round it to 8,392,802, and the actual VCO frequency will be 7,650,024,998.19
Hz, an error of -1.81Hz or about 2 parts in 2-10.
Here we program the 16 bit Nint = “Reg 04h”= 76d = 4Ch = 0000 0000 0100 1100 and the 24 bit Nfrac = 8,392,802d =
801062h = 1000 0000 0001 0000 0110 0010
In addition to the above frequency programming words, the fractional mode must be enabled using the frac register.
Other DsM configuration registers should be set to the recommended values supplied with the product evaluation
board or available from applications support.
Exact frequency Mode
The absolute frequency precision of a fractional frequency PLLs is normally limited by the number of bits in the frac-
tional modulator. For example a 24 bit fractional modulator has frequency resolution set by the phase detector (PD )
comparison rate divided by 224. In the case of a 50MHz PD rate, this would be approximately 2.98 Hz, or 0.0596 ppm.
In some applications it is necessary to have exact frequency steps, and even an error of 3Hz cannot be tolerated. In
some fractional PLLs it is necessary to shorten the length of the accumulator (the denominator or the modulus) to ac-
commodate the exact period of the step size. The shortened accumulator often leads to very high spurious levels at
multiples of the channel spacing, fstep = fPD/Modulus. For example 200kHz channel steps with a 10MHz PD rate re-
quires a modulus of just 50. The HMC method achieves the exact frequency step size while using the full 24 bit modu-
lus, thus achieving exact frequency steps with very low spurious and a high comparison rate, which maintains excellent
phase noise.
Exact frequency steps can be achieved only when the PD rate and the desired frequency step size are related by an in-
teger multiple. More precisely, the greatest common divisor, (GCD) of the PD rate and the desired frequency step size
must be an integer, and that integer must be less than 214-1 or 16,383.
As an example suppose that we want to achieve:
a. exact channel step size of fstep= 100kHz.
b. Reference Crystal fxtal = 61.44MHz
c. Phase Detector (PD) Rate fpd =61.44MHz
d. Channel 1 Frequency, fvco(CH1) = 2000.200 MHz
(EQ 8)
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